Technical Sessions

Sponsored by:


PRIME 2017 and SMACD 2017 Technical Session Programme:

Tuesday, June 13th
10:20-12:00 Emerging and Non-CMOS Technologies I
Room #1 - VULCANO
 Chair: Dr. S. Lombardo, CNR, IMM, Italy

Spin Torque Oscillator Based BFSK Modulation

R. Ma1, A. Purbawati2, M. Kreissig1, F. Protze1, A. Ruiz-Calaforra2, J. Hem2, U. Ebels2, F. Ellinger1

1TU Dresden, Germany; 2SPINTEC, France

This work presents a spin torque nano-oscillator (STNO) based binary frequency shift keying (BFSK) modulation schema implemented on a printed circuit board (PCB). Maximal input data rate reaches 20 Mbit/s. Depending on the STNO used, carrier frequency can range from 1 to 10~GHz. Both DC and AC currents flowing through the STNO can be tuned between 0 to 4 mA. Using one magnetic tunnel junction (MTJ) STNO, a 380 MHz frequency shift around the center frequency 9 GHz was observed, when the modulated current was toggled between 0.8 mA and 1.2 mA at a rate of 20 Mbit/s. This is the first work demonstrating that the STNOs are applicable for BFSK modulation on the wireless application level.


3D Design of a pNML Random Access Memory

A. Ferrara1, U. Garlando1, G. Santoro1, M. Zamboni1

1Politecnico di Torino, Italy

Among various emerging technologies, Nano Magnetic Logic (NML) is the one that may represent, in future, a replacement of CMOS for many reasons. In the last years, researchers have been conducting experiments to understand the properties and potentialities of this novel technology. NML can be used to build any kind of logic circuit and, because of its intrinsic magnetic nature, it is perfectly suitable to store data. However, the exploration of NML structures used as memories is very poor. In this paper, we propose the design of a 4x4 memory entirely based on perpendicular NML (pNML) technology. Magnets are placed onto two different overlapped layers to avoid routing congestion. The novelty introduced by this design is a distributed and modular memory cell that enables the design of highly regular memory structures optimized in terms of area occupation and write and read latency. The entire memory was also modeled in VHDL (VHSIC Hardware Description Language) and simulated to demonstrate its functional correctness.


Solution Processing of Silver Nanowires for Transparent Heaters and Flexible Electronics

M. Bobinger1, V. Dergianlis1, A. Albrecht1, M. Haider1, Q. Hirmer1, M. Becherer1, P. Lugli2

1TU Munich, Germany; 2Free University of Bozen-Bolzano, Italy

We present the solution-based synthesis of silver nanowires (AgNWs) with an aspect ratio over 400 in a short growth time of 20 min. The addition of potassium chloride (KCl) during the growth regulates the supply of silver atoms and leads to an agglomerate-free and well-dispersed solution. Via a facile and scalable deposition technique, i.e. spray-coating, the AgNWs are deposited to transparent electrodes (TEs) on flexible or glass substrates. Without any post-treatment such as sintering that can harm the substrate, the films show a high transparency at a low sheet resistance. The TEs are characterized as transparent heaters in terms of their infrared, transient thermal and electrical properties up to a working temperature of 130 deg. C. For the use in flexible electronics, an AgNW-film on a polyvinyl chloride (PVC) substrate is tested under operation for 10000 bending cycles and shows only a slight increase in resistance.


Stochastic Weight Updates in Phase-Change-Memory-Based Synapses and Their Influence on Artificial Neural Networks

I. Boybat1, M. Le Gallo1, T. Moraitis1, Y. Leblebici2, A. Sebastian1, E. Eleftheriou1

1IBM Research Zurich, Switzerland; 2EPFL, Switzerland

Artificial neural networks (ANN) have become a powerful tool for machine learning. Resistive memory devices can be used for the realization of a non-von Neumann computational platform for ANN training in an area-efficient way. For instance, the conductance values of phase-change memory (PCM) devices can be used to represent synaptic weights and can be updated in-situ according to learning rules. However, non-ideal device characteristics pose challenges to reach competitive classification accuracies. In this paper, we investigate the impact of granularity and stochasticity associated with the conductance changes on ANN performance. Using a PCM prototype chip fabricated in the 90nm technology node, we present a detailed experimental characterization of the conductance changes. Simulations are done in order to quantify the effect of the experimentally observed conductance change granularity and stochasticity on classification accuracies in a fully connected ANN trained with backpropagation.


Analysis of Array Biasing in Crosspoint Memories for Leakage Power Minimization

Y. Belay1, A. Cabrini1, G. Torelli1

1University of Pavia, Italy

Due to the recent development of resistance- switching memories, crosspoint array has become an attractive architecture to obtain high cell density. However, crosspoint arrays suffer from sneak current paths and voltage drops on interconnect lines, which lead to various challenges such as exces- sive leakage power, write failure, write disturbance and reduction of read margin. In this paper we demonstrate that the actual bias scheme, which ensures minimum leakage power consumption, is generally a function of array size and nonlinearity of the selector. By considering a generic x bias scheme (unselected wordline biased to x  VW ) and by employing a mathematical model to accurately estimate the leakage power, we study how the bias scheme can be designed for minimum leakage power consumption for a wide range of array sizes and selector nonlinearities. We demonstrate that x, which gives minimum power consumption lies somewhere between the 1/3 and 1/2.

10:20-12:00 Sensing Systems I
Room #2 - PANAREA
 Chair: Prof. G. Ferri, University of L'Aquila, Italy

A MOX Gas Sensors Resistance-to-Digital CMOS Interface with 8-Bit Resolution and 128-dB Dynamic Range for Low-Power Consumer Applications

F. Ciciotti1, C. Buffa2, R. Gaggl2, A. Baschirotto1

1University of Milano Bicocca, Italy; 2Infineon Technologies, Austria

In this paper an interface circuit for MOX gas sensor is presented. It is based on a resistance-to-frequency converter and improves existing solutions in term of performance (offset) and power efficiency. The resistive range covered is 100Ω-1MΩ, with an equivalent 8-bit precision in a total measurement time of 1 second. This corresponds to a dynamic range of about 128dB. Power consumption and design strategy are optimized for mass production targeting consumer applications. The interface is implemented in a standard CMOS 130nm technology with an area of 125000 μm2 and 450μA of current consumption.


Compressive Image Sensor Architecture with On-Chip Measurement Matrix Generation

M. Trevisi1, R. Carmona-Galan1, A. Rodriguez-Vazquez1

1Instituto de Microelectronica de Sevilla and University of Sevilla, Spain

A CMOS image sensor architecture that uses a cellular automaton for the pseudo-random compressive sampling matrix generation is presented. The image sensor employs in-pixel pulse-frequency modulation and column wise pulse counters to produce compressed samples. A common problem of compressive sampling applied to image sensors is that the size of a full-frame compressive strategy is too large to be stored in an on-chip memory. Since this matrix has to be transmitted to or from the reconstruction system its size would also prevent practical applications. A full-frame compressive strategy generated using a 1-D cellular automaton showing a class III behavior neither needs a storage memory nor needs to be continuously transmitted. In-pixel pulse frequency modulation and up-down counters allow the generation of differential compressed samples directly in the digital domain where it is easier to improve the required dynamic range. These solutions combined together improve the accuracy of the compressed samples thus improving the performance of any generic reconstruction algorithm.


A Mixed-Signal Multi-Functional System for Current Measurement and Stress Detection

A. D'Amico1, C. Djelassi2, O. Barbu2, D. Haerle3, L. Petruzzi4, A. Baschirotto1

1University of Milano Bicocca, Italy; 2Infineon Technologies, Austria; 3KAI, Austria; 4Haerl, Austria

This paper presents the development of a mixed-signal multi-functional system for current measurement and electrical stress detection. The system is composed of a tracking ADC and a double range (a coarse and a fine one) current-steering DAC. The coarse range, designed for the full-scale input values [0A:108A], has a 5b resolution and it is used for the stress detection feature. The fine range is for lower input current values [4A:14A] and it is used for the current measurement, where more accuracy is required. With respect to the full-scale, the resolution of the fine range is 8b.


A Mixed-Signal ASIC for the Readout of Gas Electron Multiplier Detectors

F. Cossio1

1Politecnico di Torino and INFN Torino, Italy

TIGER (Turin Integrated Gem Electronics for Readout) is a 64-channel front-end ASIC developed to readout the new inner tracking detector of the BESIII experiment, carried out at BEPCII in Beijing. The detector is planned to be installed during the 2018 upgrade and features an innovative three-layer triple-CGEM (Cylindrical Gas Electron Multiplier) with analog readout. With this type of readout, it is possible to implement a charge centroid method that allows to improve the spatial resolution while keeping the channels to a more manageable number of about 10000. The channels are readout by 160 TIGER ASICs, providing time and energy measurements with a fully-digital output. The charge measurement is obtained either from the time-over-threshold (ToT) or the 10-bit digitization of the signal peak amplitude. The time of the event is measured by quad-buffered, low-power TDCs, based on analog interpolation techniques, with a 50ps time resolution and a sustained event rate per channel above 60 kHz.


MEMS Microphone Fully-Integrated CMOS Cap-Less Preamplifiers

M. Croce1, P. Malcovati1, A. Baschirotto2, L. Crespi3, C. De Berti3

1University of Pavia, Italy; 2University of Milano Bicocca, Italy; 3Conexant Systems, United States

A pair of completely integrated capless pre- amplifiers (not requiring external capacitance) for MEMS micro- phones are presented. The devices exploit specific circuit solutions to implement a proper dc biasing of the pre-amplifier and a low frequency (< 1 Hz) high-pass pole. The two solutions adopted are a based on a transistor in the off state (OTP) and a switched- resistor (SRP), respectively. Since the devices are supposed to operate with different silicon microphones, the pre-amplifier gain has to be programmable. In spite of the single ended configuration and independently of the gain, both pre-amplifiers achieve a signal to noise ratio (SNR) lower than −100 dB. The total harmonic distortion (THD) is lower than −80 dB for the OTP and lower than −100 dB for the SRP. The devices are implemented in a 0.18-μm CMOS technology, with a supply voltage of 1.8-V. In both cases the power consumption is 230 μW. The bandwidth of interest ranges from 20 Hz to 20 kHz. Both solutions have variable gain configurations [−6, 0, 6, 12, 18] dB.

10:20-12:00 Radio Frequency Circuits and Systems I
Room #3 - LIPARI
 Chair: Prof. C. Dehollain, Ecole Polytechnique Federale de Lausanne, Switzerland

Output Matching Network Design for Broadband Class B/J Power Amplifier

S. Boutayeb1, A. Giry1, A. Serhan1, J. Arnould2, E. Lauga-Larroze2

1CEA-LETI, France; 2University of Grenoble-Alpes, France

This paper presents a design approach for output matching network (OMN) required in continuous class B/J power amplifiers (PA). Design equations of the OMN are derived and used to design a class-B/J PA that covers the frequency band from 2.35 GHz to 3.65 GHz. The PA uses the LDMOS device available in the 130nm SOI technology from STMicroelectronics. Simulation results show that the PA has an efficiency higher than 65% while delivering an output power higher than 23.6dBm across the targeted frequency band. The maximum simulated efficiency is 74% for an output power of 24.3dBm at 3 GHz.


A TVWS LNTA with Balanced Output Employing a Low-Noise Current Multiplier

A. Coccia1, D. Manstretta1, R. Castello1

1University of Pavia, Italy

In this paper, a broadband, inductorless noise-canceling low-noise transconductance amplifier is presented. The proposed circuit is suitable for TV White-Space applications. It has a single-ended input, eliminating the need for an external balun, and a balanced output, which can be followed by a double-balanced current-switching mixer for high IIP2. The circuit is based on a common-gate stage with a feed-forward noise-canceling common-source path. High common-source transconductance improves noise but leads to unbalanced output currents. The currents are re-balanced with the help of a current multiplier, which introduces much less noise than a classic current mirror. The power consumption is only 3 mW, for a NF<2.6 dB and a good input matching (S11< -20 dB) from 100 MHz to 1GHz.


3-Path 5-6-GHz 0.25-um SiGe BiCMOS Power Amplifier on Thin Substrate

S. Oezbek1, G. Alavi1, J. Digel1, M. Grozing1, J. Burghartz1, M. Berroth1

1University of Stuttgart, Germany

This paper presents a fully integrated class-A mode Differential Power Amplifier (DPA) on a thin silicon substrate intended for being embedded into flexible electronic foil systems. A high-speed and cost-effective 95 GHz-fmax, 0.25 μm SiGe:C technology (IHP process SGB25V) is used. RF performance of DPA has been evaluated with the pre- and post-thinning measurement results at die level. The behavior of the PA has been optimized for 5-6 GHz frequency band and achieves 10.85 dB and 10 dB small-signal gain at 5.5 GHz before and after thinning, respectively. The measured large signal gain of amplifier at Pin 0 dBm is 10 dB before and 9.4 dB after thinning process. The simulated output referred 1 dB compression point is 10.76 dBm with a PAE of 15%. The PA consumes 50 mA under 1.5 V supply voltage. After thinning process, the supply current is lowered by 3 mA.


Enhanced Zero Crossing Frequency Estimation for FMCW Radar Systems

B. Al-Qudsi1, M. El-Shennawy1, N. Joram1, F. Ellinger1

1TU Dresden, Germany

This paper presents a spectral peak estimation technique for tight resources systems. Based on a basic zero crossing (ZC) frequency estimator, an enhanced ZC frequency estimation technique is proposed. The proposed technique conducts a tunable band pass filter (BPF) that relies on a primary estimation of the frequency value from another ZC block. In principle, the filter reduces the noise content of the signal, hence increasing the quality of the ZC algorithm. The technique is computationally very efficient and can be easily implemented on low cost systems. It was evaluated in a practical frequency modulated continuous wave (FMCW) ranging system. A ranging precision of around 2.24 cm was practically achieved.


NLOS Mitigation in FMCW RADAR with CLEAN Peak Detection

A. Figueroa1, B. Al-Qudsi1, N. Joram1, F. Ellinger1

1TU Dresden, Germany

A secondary frequency modulated continuous wave (FMCW) RADAR with two-way ranging can be used for indoor and outdoor positioning with high precision and accuracy. However, non-line-of-sight (NLOS) conditions lead to multipath effects that have a negative impact on the quality of ranging and positioning measurements, if the spectral analysis is not able to detect the correct line-of-sight (LOS) path. This work proposes an improved peak detection algorithm - based on CLEAN - that works on the base band spectra in each RADAR base station, in order to enable LOS path detection. In a simple ranging scenario at 3m distance, the conventional parabolic interpolation for sub-bin resolution exhibits errors of up to 1.5m (50%) for a large fraction of the measurements. The CLEAN algorithm, however, improves upon this by drastically reducing the number of outliers. In a positioning scenario, the parabolic interpolation exhibits errors between 0.2-0.8m, the CLEAN algorithm reduces this error to below 0.5m.

10:20-12:00 Layout and layout-aware synthesis
Room #4 - Plenary room
 Chair: Prof. J. Scheible, Reutlingen University, Germany

Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks

Ricardo Martins1,2, Nuno Lourenco1,2, Ricardo Povoa1,2, Antonio Canelas1,2, Nuno Horta1,2, Fabio Passos3, Rafael Castro-Lopez3, Elisenda Roca3 and Francisco Fernandez3

1Instituto de Telecomunicacoes, Lisbon, Portugal; 2Instituto Superior Tecnico, Lisbon, Portugal; 3Instituto de Microelectronica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain

In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most established computer-aided design tools available nowadays, i.e., off-the-shelf circuit simulator, electromagnetic simulator and layout extractor. The approach intends to bypass the two major bottlenecks of RF-design: the design of reliable integrated inductors and accurate layout parasitic estimates since the early stages of design process.


Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware Approach

F. Passos1, Elisenda Roca1, Rafael Castro Lopez1, Francisco V. Fernandez1, Ricardo Miguel Martins2,3, Nuno Lourenco2,3, Ricardo Povoa2,3, Antonio Canelas2,3 and Nuno Horta2,3

1Instituto de Microelectronica de Sevilla, CNM, CSIC and Universidad de Sevilla, Spain; 2Instituto de Telecomunicacoes, Lisbon, Portugal; 3Instituto Superior Tecnico, Lisbon, Portugal

This paper focuses on the systematic design of voltage controlled oscillators (VCO), a commonly used radiofrequency (RF) electronic circuit. RF circuits are among the most difficult analog circuits to design due to its trade-offs and high operation frequencies. At such operation frequencies, layout parasitics and accurate passive component characterization become of upmost importance, causing redesign iterations if they are not considered by the designer. To avoid this problem, and reduce the design time, this paper presents a systematic design of a VCO, entailing layout parasitics and accurate characterization of passive components from early design stages. Results clearly illustrate the benefit of this strategy.


MESH: Explicit and Flexible Generation of Analog Arrays

Benjamin Prautsch1, Uwe Eichler1, Torsten Reich1 and Jens Lienig2

1Fraunhofer IIS/EAS, Institute for Integrated Circuits, Division Engineering of Adaptive Systems, Germany; 2Dresden University of Technology, Germany

Analog layout design is a costly and error-prone task since analog synthesis is still far from applicable. It is expected that procedural and parameterizable bottom-up generators managing constructive tasks will be part of future synthesis flows. Generators contain expert knowledge implicitly within complex and hard-to-understand source code. Due to a lack of explicit layout definition and uncaptured design intent, generator layouts can hardly be adapted by constructive algorithms directly. Thus, synthesis flows need to adapt layout blocks by varying generator parameters which results in computation-expensive optimization. This paper introduces MESHA - a software structure to define detailed and flexible layout generators explicitly. Using MESH, just a few lines of code describe complex layouts while all relations and design intents, such as element positions and routing styles, are captured through abstract commands. As a result, generators are created fast with less programming errors, and constructive algorithms can modify the generator structure directly.


Analog Layout Placement Retargeting using Satisfiability Modulo Theories

Aya Mohamed1, Mohamed Dessouky1 and Sherif Saif2

1Mentor Graphics, Egypt; 2Computer and Systems Department, Electronics Research Institute, Egypt

This paper presents an efficient methodology for automatic analog layout process retargeting, which fits in the current design flow. It relies on two concepts: First, the reuse of source layout heuristics and matching considerations through device placement constraint extraction. This allows an automatic layout reconstruction using foundry Parameteric Cells (PCells) of the target process, as in the current design flow. Second, feeding those constraints to an analog layout automatic placer based on Satisfiability Modulo Theories (SMT). Besides conserving the source layout topology, this also allows generating multiple layout options in case of large changes of device dimensions and/or requiring a new aspect ratio in the target process. Two test cases of a Miller-OTA and a two-stage comparator demonstrate the proposed flow.


A Novel Approach for Automatic Common-Centroid Pattern Generation

Vadim Borisov1, Kerstin Langner1, Juergen Scheible1 and Benjamin Prautsch2

1Reutlingen University, Germany; 2Fraunhofer IIS/EAS, Fraunhofer Institute for Integrated Circuits, Division Engineering of Adaptive Systems, Dresden, Germany

This paper introduces a novel placement methodology for a common-centroid (CC) pattern generator. It can be applied to various integrated circuit (IC) elements, such as transistors, capacitors, diodes, and resistors. The proposed method consists of a constructive algorithm which generates an initial, close to the optimum, solution, and an iterative algorithm which is used subsequently, if the output of constructive algorithm does not satisfy the desired criteria. The outcome of this work is an automatic CC placement algorithm for IC element arrays. Additionally, the paper presents a method for the CC arrangement evaluation. It allows for evaluating the quality of an array, and a comparison of different placement methods.

13:00-15:00 Modeling, Optimization, and Characterization I
Room #1 - VULCANO
 Chair: Prof. N. Horta, University of Lisbon, Portugal

Low-Power Optimization of a Pixel Array Architecture for Next Generation High Energy Physics Detectors

S. Marconi1,4, T. Hemperek2, P. Placidi3, A. Scorzoni3, E. Conti4, J. Christiansen4

1University of Perugia and INFN Perugia, Italy; 2University of Bonn, Germany; 3University of Perugia, Italy; 4CERN, Switzerland

A large scale pixel readout chip is being designed by the RD53 Collaboration, in order to prove the suitability of 65 nm technology for the extreme operating conditions foreseen for the High Luminosity upgrades of the ATLAS and CMS experiments at CERN. The use of advanced digital design and simulation tools is essential to guide architectural and implementation choices for the design and optimisation of pixel chips which will be powered from a serial powering scheme. In this work, low power design techniques are reviewed and critically selected based on the requirements of the target application. Chosen techniques are adopted and results of the low power optimisation are presented for a basic unit of the system.


Formal Verification of a Transistor PCell

K. Langner1, J. Scheible1

1Reutlingen University, Germany

Layout generators, commonly denoted as PCells (parameterized cells), play an important role in the layout design of analog ICs (integrated circuits). PCells can automatically create parts of a layout, whose properties are controlled by the PCell parameters. Any layout, whether hand-crafted or automatically generated, has to be verified against design rules using a DRC (design rule check) in order to assure proper functionality and producibility. Due to the growing complexity of today's PCells it would be beneficial if a PCell itself could be ensured to produce DRC clean layouts for any allowed parameter values, i.e. a formal verification of the PCell's code rather than checking all possible instances of the PCell. In this paper we demonstrate the feasibility of such a formal PCell verification for a simple NMOS transistor PCell. The set from which the parameter values can be chosen was found during the verification process.


PCB RF Probe Landing Pads for Multiline Deembedding

S. Sattler1, M. Gadringer1, F. Gentili1, A. Alterkawi1, W. Boesch1

1TU Graz, Austria

The interface between a probe station and an active or passive component on a printed circuit board is of great importance for RF systems operating in the mm-wave frequency range. The landing pads provide the transition between a coplanar measurement device and a microstrip interface. This paper addresses the design issues of such landing pads focusing on finding the optimal design enabling multiline deembedding with a measurement error better than 0.1dB.


A Comparison of Simulation Strategies for Estimating Phase Noise in Oscillators

S. Galeone1, M. Kennedy1

1University College Cork, Ireland

This paper compares three simulation methods to calculate the Gamma functions in oscillators. The first method uses the ISF approach while, the second and the third are based on the PPV approach. The equivalence of the three methods is confirmed with two examples: a Van Der Pol oscillator and a ring oscillator. It is then proposed the use one of them as the faster in terms of simulation time, providing designers with a very powerful, fast and easy procedure to identify and separate contributors to phase noise in oscillators.


Phase Noise in Fractional-N Frequency Synthesizers Employing Successive Requantizers and MASH-SQ Hybrids

Y. Donnelly1, M. Kennedy1

1University College Cork, Ireland

Noise-shaping quantizers are used in fractional-N PLLs to provide a fractional-mean modulation signal to the loop divider. A drawback to this method is the introduction of phase noise due to the changing divide ratio. Noise shaping techniques are typically employed, but have been shown to produce spurs in the presence of loop nonlinearities. An alternative to the traditional MASH DDSM has been introduced in the form of the Successive Requantizer (SQ), which can offer better spurious performance at the expense of area. The MASH-SQ Hybrid combines both approaches to achieve the performance of the SQ with a much reduced implementation cost. In this paper, we summarise the properties of the SQ and a method for estimating the phase noise introduced, before deriving the minimum number of requantization stages required to mask an input modulation signal, and thus present an expression for the optimum MASH-SQ Hybrid size.


Design and Numerical Characterization of a Low Voltage Power MOSFET in 4H-SiC for Photovoltaic Applications

G. De Martino1, F. Pezzimenti1, F. Della Corte1, G. Adinolfi2, G. Graditi2

1University of Reggio Calabria, Italy; 2ENEA Napoli, Italy

Higher efficiency in photovoltaic (PV) conversion calls for the use of small Maximum Power Point Trackers (MPPT) to be placed on board the PV modules. Such circuits require in turn power transistors with low energy losses, high switching speed and blocking voltages lower than 150 V. Thus, starting from a conventional 4H-SiC power MOSFET, a novel device for photovoltaic applications has been designed and numerically simulated in order to determine its on-state resistance (RON) for different device structures and bias voltages. The resulting value of RON is compared to that of a commercial Si-based MOSFET performing the same breakdown voltage.

13:00-15:00 Special Session on "Modeling and circuit design in electroporation"
Room #2 - PANAREA
 Chair: Proff. P. Lamberti, M. Rebersek and S. Romeo

Modeling and optimization of Blumlein nanosecond pulse generator for experiments on planar lipid bilayers

Matej Rebersek, Eva Pirc, Damijan Miklavcic and Peter Kramar

University of Ljubljana, Slovenia

Although electroporation protocols are common in biomedicine and biotechnology, the fundamental molecular-scale mechanisms involved in electroporation are still not completely understood. Therefore, molecular dynamics (MD) simulations of small patches of planar lipid bilayers (PLB) and experimentally formed PLB are used to model the cell membrane and to explain the electroporation process. However, in addition to the size difference, there is also a significant time gap between this two modeling methods. MD simulates processes up to nanoseconds while experimentally formed PLB are used to detect microsecond processes. In the presented work we model and optimize Blumlein nanosecond generator with pulse forming networks (PFN) for application of nanosecond pulses on PLB, where PLB chamber electrically represents low conductance and high capacitance. Blumlein nanosecond generator with PFN is suitable for adjusting the impedance of the generator to the impedance of the load. The challenge of generating nanosecond pulses on PLB can be addressed with careful designing of the pulse generator architecture and selecting appropriate electrical components. Numerical approaches, such as SPICE, can be a great help during development of pulse generators by either verification of its configuration or defining values of electrical components in order to obtain desired pulse characteristics.


Frequency spectra of induced transmembrane potential correlate with nanosecond bipolar pulse cancellation of electropermeabilization

Caterina Merla1, Andrei Pakhomov2 and P. Thomas Vernier2

1ENEA, Italy; 2Frank Reidy Research Center for Bioelectrics, Old Dominion University, USA

A simple prediction method for the bipolar pulse cancellation effect is proposed, based on analysis of single-cell transmembrane potential frequency spectra for a variety of unipolar and bipolar input signals in the nanosecond and microsecond time scales. Our evaluations are in good agreement with experimental results for electropermeabilization-induced Ca2+ influx using 300 ns, 750 kV/m pulses.


Numerical estimation of a 10 nanosecond pulse effects on non-uniformly distributed liposomes

Elena Della Valle1, Francesca Apollonio1, Micaela Liberti1, Agnese Denzi2 and Lluis M Mir3

1Sapienza, University of Rome, Italy; 2Istituto Italiano di Tecnologia, Rome, Italy; 3CNRS, Univ. Paris-Sud, Gustave Roussy, Universite Paris-Saclay, Villejuif, France

Nano-systems, often used in biomedical applications for the treatment of a broad category of illnesses, represent one of the nanomedicine approaches recently proposed to target specific drugs only in the region where the disease has been developed. Recently the use of this technique has been proposed with electropulsation, hence taking advantage of the enhanced permeabilization of the cell membrane and simultaneously control the release of the encapsulated drug by the nano-system. In this work, we focus our attention on the study of liposomes nano-systems controlled by the nanosecond pulses electric fields through a microdosimetric approach. The aim is to analyse the electric field necessary to porate a nonuniform distribution of 400 nm liposomes. The work has been carried out by randomly placing 30 liposomes between two electrodes with the application of a 10 nano-second electric field pulse.


A coarse 3D lattice network modeling electroporation phenomenon in an excitable cell

Patrizia Lamberti, Nunziante Citro, Luigi Egiziano and Vincenzo Tucci

DIEM, University of Salerno, Italy

A spherical excitable cell immersed in an electrolyte and subjected to an electric field is considered to study its behavior for Electro-Chemotherapy Treatments (ECT). The total volume is discretized with a three-dimensional lattice to which an electrical network, modeling both the passive and linear behavior of the external electrolyte and of the cytosol than the complex behavior of the ionic fluxes through the cell membrane, is associated. The Electroporation Phenomenon (EP) is considered by modeling the electrically induced pores with a voltage controlled current source governed by the dynamic of the pore density, N, and the current in a single pore. The physiological Action Potential (AP) of a Normal Rat Kidney (NRK) cell is reproduced and the EP is analyzed by looking at the transmembrane voltage (TMV) of the cell exposed to a trapezoidal Pulsed Electric Field (PEF) with a duration of 100us, a rise/fall time of 4us and amplitude of 750V/cm.


Microdosimetry for Pulsed E Fields in a Realistic Models of Cells and Endoplasmic Reticulum

Agnese Denzi1, Hanna Hanna2, Franck M. Andre2, Lluis M. Mir2, Francesca Apollonio3 and Micaela Liberti3

1Istituto Italiano di Tecnologia, Italy; 2CNRS, Univ. Paris-Sud, Universite Paris-Saclay, Gustave Roussy, France; 3Sapienza, University of Rome, Italy

Microsecond pulsed electric fields (usPEFs) with amplitude of tens of kV/m are used to permeabilize the plasma membrane whereas nanosecond pulsed electric fields of MV/m also permeabilize cell internal structures, such as the endoplasmic reticulum. In this work, a numerical realistic model of cell and its reticulum has been realized to study the use of usPEFs also for the permeabilization of this internal structure.


Electrical resistance in inhomogeneous samples during electroporation

Luca Giovanni Campana1,2, Paolo Di Barba3, Maria Evelina Mognaschi3, M. Bullo4, Fabrizio Dughiero4, Michele Forzan4, Paolo Sgarbossa4, Eugenia Spessot4 and Elisabetta Sieni4

1Veneto Institute of Oncology IOV-IRCCS, Padua, Italy; 2DISCOG, University of Padua, Italy; 3Department of Electrical, Computer and Biomedical Engineering, University of Pavia, Italy; 4University of Padua, Department of Industrial Engineering, Italy

In electrochemotherapy (ECT), electric field is applied by means of needle pairs to the tumor tissue in order to permeabilize cell membranes and, as a consequence, enhance the effects of chemotherapeutic drugs. The target tissue is not homogeneous and the electric field, generated by the needle pairs, is strongly affected by the specific electrical characteristics of different tissues. This paper analyzes the effect of tissue inhomogeneity by means of numerical models and suitable experiments.

13:00-15:00 Special Session on "Reliability of electronic devices and circuits"
Room #3 - LIPARI
 Chair: Proff. M. Nafria and F. V. Fernandez

Advanced Integration of Variability and Degradation in RRAM SPICE Compact Models

Fernando Garcia-Redondo, Marisa Lopez-Vallejo and Carlos A. Lopez Barrio

IPT Center, Universidad Politecnica de Madrid, Spain

Variability and degradation in RRAM devices involve complex physical mechanisms that depend on the device, environment and programming/read operation. The development of solid and accurate compact models, ready to be used in standard circuit simulators, requires the meticulous emulation of this kind of non-ideal effects. In this work we present an advanced approach for the emulation of complex variability and degradation effects in SPICE compacts models. Without requiring compiled components - such as Verilog-A or CMI code - the proposed solution can be adapted to any kind of memristor model providing full support to the emulation of these intricate behaviors. Thorough experiments illustrate the capabilities of the presented approach. There, we make use of a physical SPICE model that emulates behavioral dependence on the device cycling, simulation time and stress levels. After applying the proposed techniques, we obtain an enhanced model properly aware of the the device’s non-ideal behavior.


A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging

Javier Diaz-Fortuny1, Javier Martin-Martinez1, Rosana Rodriguez-Martinez1, Montse Nafria-Maqueda1, Rafael Castro-Lopez2, Elisenda Roca-Moreno2, Francisco V. Fernandez-Fernandez2, Enrique Barajas-Ojeda3, Xavier Aragones3 and Diego Mateo-Pena3

1Universitat Autonoma de Barcelona (UAB), Spain; 2IMSE-CNM (CSIC/Universidad de Sevilla), Spain; 3Universitat Politecnica de Catalunya (UPC), Spain

In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.


Review: Analog Design Methodologies for Reliability in Nanoscale CMOS Circuits

Engin Afacan1, Mustafa Berke Yelten2 and Gunhan Dundar1

1Bogazici University, Turkey; 2Istanbul Technical University, Turkey

In modern CMOS technology, local electrical stress has substantially increased as device geometries scaled down more aggressively compared to supply voltages. As a result, time-dependent degradation mechanisms (aging phenomena) became an important performance problem, which leads to a considerable lifetime reduction in manufactured integrated circuits. Combination of these aging phenomena with process variations has made reliability a major design objective. In analog circuits, different approaches have been proposed to mitigate the performance challenges related to device reliability. This paper discusses aging in CMOS technology and reviews reliability-aware analog circuit design methodologies for nanoscale circuits.


Variation- and Degradation-Aware Stochastic Behavioral Modeling of Analog Circuit Components

Maike Taddiken, Theodor Hillebrand, Steffen Paul and Dagmar Peters-Drolshagen

University of Bremen, Germany

Process variation and aging effects influence the performances of integrated circuits in modern technology nodes. In this paper, a method is proposed to build a behavioral model to represent the influences of process variation, aging and operational parameters on circuit performances. The variability of performance is represented using distribution functions while Response Surface Models (RSM) are used to describe the dependence of the distribution's moments on operational parameters. Compared to other approaches, less parameters have to be included in the RSM therefore reducing the complexity. This enables a fast Monte-Carlo analysis with aging analysis on a behavioral level. The method is evaluated for a voltage reference circuit and an operational amplifier showing a good representation of the variability and reaching a very good speedup of simulation time.


Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells

Javier Martin Martinez1, Rosana Rodriguez1, Montserrat Nafria1, Gabriel Torrens2, Sebastia Bota2, Jaume Segura2, Francesc Moll3 and Antonio Rubio3

1Universitat Autonoma de Barcelona, Spain; 2Universitat de les Illes Balears, Spain; 3Universitat Politecnica de Catalunya, Spain

Random Telegraph Noise (RTN) effects are investigated in 65nm SRAM cells by using a new characterization method that provides a significant measurement time reduction. The variability induced in commercial SRAM cells is derived by applying statistical and physics based Montecarlo modeling to the experimental data. Results show that RTN can have a significant impact on the memory write operations and should therefore be taken into account during the memory design phase.


20nm FinFET-based SRAM Cell: Impact of Variability and Design Choices on Performance Characteristics

Shushanik Karapetyan and Ulf Schlichtmann

Technical University of Munich, Germany

The relentless scaling of semiconductor technology has resulted in dramatic performance improvements of Integrated Circuits (ICs). However, traditional planar CMOS technology seems to have reached its limit. To continue with Moore's law, FinFET technology has shown to be a viable solution. Process variations are still relevant, however. Therefore, it is crucial to study their impact on circuit performance. This paper explores design choices for 20nm FinFET-based SRAM cells and analyzes the impact of process variations on the performance characteristics of the SRAM cell.

13:00-15:00 Digital Circuits and Sub-Systems
Room #4 - Plenary room
 Chair: Prof. G. Palumbo, University of Catania, Italy

Low-Power Approximate MAC Unit

D. Esposito1, A. Strollo1, M. Alioto2

1University of Napoli "Federico II", Italy; 2National University of Singapore, Singapore

Sacrificing exact calculations to improve digital circuit performance is at the foundation of approximate computing. In this paper, an approximate multiply-and-accumulate (MAC) unit is introduced. The MAC partial product terms are compressed by using simple OR gates as approximate counters; moreover, to further save energy, selected columns of the partial product terms are not formed. A compensation term is introduced in the proposed MAC, to reduce the overall approximation error. A MAC unit, specialized to perform 2D convolution, is designed following the proposed approach and implemented in TSMC 40nm technology in four different configurations. The proposed circuits achieve power savings more than 60%, compared to standard, exact MAC, with tolerable image quality degradation.


An Automated S-Box Optimization Based on Composite Field Arithmetic

L. Sarti1, L. Baldanzi1, B. Carnevale1, L. Fanucci1

1University of Pisa, Italy

In recent years, the information technology world have faced broad security issues due to the large amount of data flowing over the network. HW security solutions are often preferred in contexts where an high level of performance is required. Multiple HW implementation of the Advanced Encryption Standard can be found in literature. Although several optimization methods based on optimum composite field isomorphic mappings have been shown and evaluated, there is a lack of results coming from automatic synthesis tools. This work presents an optimization of the AES core using synthesis tools that exploits composite field arithmetic for the SBox module implementation. The Parametric syntheses are repeated for both FPGA technology, using Xilinx Vivado on a Xilinx Zynq 7000 board, and for Standard Cell technology, using Synopsys Design Compiler and 40nm CMOS Standard Cell libraries. Results highlight the discrepancies between analytic and synthesized optimum parameters.


Improved StrongARM Latch Comparator: Design, Analysis and Performance Evaluation

A. Almansouri1, A. Alturki1, A. Alshehri1, T. Al-Attar1, H. Fariborzi1

1King Abdullah University of Science and Technology, Saudi Arabia

This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.


Hardware Support for UNUM Floating Point Arithmetic

A. Bocco1, Y. Durand1, F. De Dinechin2

1CEA-LETI, France; 2INSA Lyon, France

The Universal NUMber, or UNUM, is a variable length floating-point format conceived to substitute the current one defined in the IEEE 754 standard. UNUM is able, through an internal algebra based on interval arithmetic, to keep track of the precision during operations, offering better result reliability than IEEE 754. This work discusses the implementation of UNUM arithmetic and reports hardware implementation results of some of the UNUM operators.


Introducing Approximate Memory Support in Linux Kernel

G. Stazi1, F. Menichelli1, A. Mastrandrea1, M. Olivieri1

1University of Roma "La Sapienza", Italy

This paper describes the implementation of approximate memory support in Linux operating system kernel. The new functionality allows the kernel to distinguish between normal memory banks, which are composed by standard memory cells that retain data without corruption, and approximate memory banks, where memory cells are subject to read/write faults with controlled probability. Approximate memories are part of the wider research topic regarding approximate computing and error tolerant applications, in which errors in computation are allowed at different levels (data level, instruction level, algorithmic level). In general these errors are the result of circuital or architectural techniques (i.e. voltage scaling, refresh rate reduction) which trade off energy savings for the occurrence of errors in data processing. The ability to support approximate memory in the OS is required by many proposed techniques which try to save energy raising memory fault probability, but an actual implementation on the Linux OS kernel has never been proposed. In this paper we provide a description of how approximate memory management can be added to Linux kernel, allowing it to be aware of exact (normal) and approximate physical memories, managing them as a whole for the common part (e.g. optimization algorithms, page reuse) but distinguishing them in term of allocation requests and page pools management. The new kernel has been built and extensively tested on a hardware x86 platform, showing the correctness of the implementation and of the fallback allocation policies.


Area Efficient DST Architectures for HEVC

M. Masera1, M. Martina1, G. Masera1

1Politecnico di Torino, Italy

This work analyses the actual throughput of the Discrete Sine Transform (DST) stage in a realistic HEVC encoder, which executes the rate-distortion optimization algorithm to achieve high compression quality. Then, a low complexity DST factorization, where all the integer multiplications are substituted with add-and-shift operations, is exploited to design an efficient 1D-DST core. The proposed 1D-DST core is employed to derive two area efficient architectures, namely Folded and Full-parallel, for computing the 4x4 2D-DST in HEVC. Finally, the proposed 2D-DST architectures are synthesized on a 90-nm standard cell technology to support the actual target throughput required to encode 4K UHD @30fps video sequences, showing better area efficiency with respect to existing DST architectures for HEVC.

16:40-18:00 Power electronics and nonlinear systems
Room #1 - VULCANO
 Chair: Prof. N. Femia, University of Salerno, Italy

Extended Analysis of Idealized Class-E Operation with Finite DC-feed Inductance and Preservation of Zero Volt Switching at Variable Load

Martin Kreißig and Frank Ellinger

Technische Universitat Dresden, Germany

This work comprises an extended and comprehensive evaluation of idealized class-E operation with ?nite DC feed inductance. It exhibits an analysis of varying switching duty cycle as well as varying switch voltage slope at switch-on time. As a result of this special cases for idealized class-E operation able to maintain efficient zero-volt switching while the load resistance changes is revealed which can be utilized for speci?c RF outphasing systems. Furthermore and as to the best knowledge of the authors we will present the highest possible value which has ever been calculated for the power capability of idealized class-E operation namely 0.1092.


Chirp Design in a Pulse Compression Procedure for the Identification of Non-Linear Systems

Pietro Burrascano1, Stefano Laureti1, Luca Senni1, Giuseppe Silipigni1, Riccardo Tomasello1 and Marco Ricci2

1University of Perugia, Italy; 2University of Calabria, Italy

The Hammerstein model of a nonlinear systems can be efficiently identified by means of a technique based on pulse compression. The procedure relies on the properties of the exponential chirps, adopted as excitation signals. The present paper proposes to include the initial phase of the chirp, together with its time duration and frequency extremes, among the parameters to design the excitation signal. Considering this widened set of design parameters, we identify the constraints that the excitation signal must meet to carry out an accurate identification. The paper shows that introducing the initial phase as further degree of freedom, adds flexibility to the design process and allows for the use of much shorted chirp signals, making measurements faster and reliable. The experimental results reported demonstrate the validity of the constraints identified and show that, choosing appropriate combinations of the parameters, very short chirp accomplish the phase constraint needed for an accurate modelling of the non linear system.


Optimizing Power Converters with Partially Saturated Inductors by Evolutionary Algorithms

Kateryna Stoyka, Nicola Femia and Giulia Di Capua

DIEM, University of Salerno, Italy

This paper investigates the optimization of power converters using ferrite inductors in Sustainable Saturation Operation (SSO), performed by means of an Evolutionary Algorithm (EA). The EA is adopted to identify viable optimal solutions providing a trade-off among efficiency, inductor volume, reliability and electromagnetic emissions. Three non-isolated low-power converters of different voltage and current ratings and based on buck, boost and buck-boost topologies, have been considered for the investigation. The results show that the EA is able to identify design solutions achieving best efficiency, volume, reliability and emissions performances with inductors in SSO.


Ferrite Inductor Models for Switch-Mode Power Supplies Analysis and Design

Giulia Di Capua1, Nicola Femia1, Kateryna Stoyka1, Matteo Lodi2, Alberto Olivieri2 and Marco Storace2

1DIEM, University of Salerno, Italy; 2DITEN, University of Genoa, Italy

This paper discusses some models useful to analyze ferrite inductors operating in partial saturation in Switch-Mode Power Supplies (SMPSs). Inductance vs current curves are needed to assess if the level of saturation is sustainable for the inductor, in order to achieve SMPS volume reduction. The models discussed in the paper are generated from experimental voltage and current waveforms of the inductor in SMPSs. Two dual approaches are presented, based on the local and global characterization of the inductor under small- and large-amplitude current ripple conditions. The resulting curves provide inductor current prediction in agreement with experimental data.

16:40-18:00 Data Converters I
Room #2 - PANAREA
 Chair: Prof. F. Maloberti, University of Pavia, Italy

Design of a Low-Power Potentiostatic Second-Order CT Delta-Sigma ADC for Electrochemical Sensors

J. Aymerich1, M. Dei1, L. Teres2,1, F. Serra-Graells2,1

1IMB-CNM (CSIC), Spain; 2Autonomous University of Barcelona, Spain

A low-power potentiostatic second-order continuous-time delta-sigma modulator architecture for electrochemical amperometric sensors is presented. The architecture takes advantage of the intrinsic double-layer capacitance of the sensor used as an integrator stage to have a compact and energy efficient conversion of the electrochemical signal. The addition of a second integrator guarantees the real potentiostat operation while introducing new design trade-offs such as stability and resolution. The circuit has been simulated in a standard 0.18 μm CMOS technology. As a proof of concept, a cyclic voltammetry based on real measurements is also presented.


A Low Power 14-Bit 1-MS/s Extended-Range Incremental ADC for High Energy Physics Experiments in 28-nm Technology

M. Elkhayat1, M. Grassi1, P. Malcovati1, A. Baschirotto1

1University of Pavia, Italy

This paper presents a 14-bit 1MS/s extended range incremental A/D converter composed by the cascade of two resettable second-order sigma-delta modulators in 28nm technology. The system is designed for applications in instrumentation electronics for particle physics. Design of the converter is reported, including feasibility study and switched capacitor implementation. Architecture simulation results including non-idealities are reported. The developed A/D converter will be used for ultra scaled technology (28nm) radiation hardness study in high energy physics experiments.


Split-Based Time-interleaved ADC with Digital Background Timing-Skew Calibration

M. Guo1, S. Sin1, S. U1, R. Martins1

1University of Macau, China

This paper presents a split-based time-interleaved (TI) ADC with digital background timing calibration for wideband applications. Each interleaved channel uses a split ADC, which adds a dimension for timing-skew error detection and correction. Thus, the complexity of digital post-processing is greatly relaxed without the use of any dummy channel. The behavioral simulations show a 28 dB and 35 dB improvements in signal-to-noise plus distortion (SNDR) and spurious-free dynamic range (SFDR) respectively, after adopting the proposed timing skew correction for a 10-bit 4GS/s ADC example.


A 3rd-Order Time-Interleaved Sigma-Delta Modulator

A. Akdikmen1, E. Bonizzoni1, F. Maloberti1

1University of Pavia, Italy

Two-path time-interleaved method applied to a third order sigma-delta modulator is presented. A domino-free solution moves a part of the required processing in the second path from digital domain to analog domain and relaxes the timing constraints of the second path ADC. Simulations show that it is possible to achieve 90 dB SNR with -6 dBFS input and 4-bit quantizer by using 1 GHz clock frequency (OSR=25) using a 65 nm CMOS technology.

16:40-18:20 Analog Circuits I
Room #3 - LIPARI
 Chair: Prof. G. Palmisano, University of Catania, Italy

A Dynamic Voltage-Combiners Biased OTA for Low-Power and High-Speed SC Circuits

R. Povoa1, A. Canelas1, R. Martins1, N. Lourenco1, N. Horta2, J. Goes3

1Instituto de Telecomunicacoes, Portugal; 2Instituto Superior Tecnico, Portugal; 3Uninova, Portugal

This paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.


Design of Current Feedback Instrumentation Amplifiers with Rail-to-Rail Input-Output Ranges

A. Catania1, S. Del Cesta1, P. Bruschi1, M. Piotto2

1University of Pisa, Italy; 2CNR IEIIT Pisa, Italy

System level modeling is applied to a recently proposed indirect current feedback (ICF) chopper instrumentation amplifier based on a Gm-C low pass filter architecture. The aim of the study is solving important limitations of the previous architecture in terms of output range and bandwidth-to-chopper frequency ratio. The possibility of obtaining a rail-to-rail input common mode range is also investigated. An improved architecture is proposed and analyzed by means of simulations that consider the main non-idealities of the building blocks.


Improved Switched-Capacitor Cell for a 3-GHz 20-GS/s Waveform Digitizing ASIC

P. Orel1, G. Varner1

1University of Hawaii at Manoa, United States

Detectors in high energy physics (HEP) that are subject to high hit rates require fast and sophisticated instrumentation. The proposed timing vertex detector (TVD) requires femtosecond resolution timing to determine the space-time coordinates of the traversing particles. One of its key components is the RFpix waveform digitizing ASIC, which is being designed to operate with an analog bandwidth of 3 GHz and sampling speed of up to 20 GS/s. The RFpix sampling architecture is based on switched capacitor arrays (SCA), which provide high channel density and low power. In this paper, analysis results of a sampling cell pertaining to a similar ASIC called PSEC4 are presented and compared to the simulation results of an improved sampling cell, designed to meet the RFpix requirements.


Reconfigurable Low Voltage Inverter-Based Sample-and-Hold Amplifier

D. Ruscio1, F. Centurelli1, P. Monsurro1, A. Trifiletti1

1University of Roma "La Sapienza", Italy

In this paper, a voltage-scalable inverter-based operational amplifier suitable to be used in a reconfigurable ADC is optimized. A very low voltage sample-and-hold (SHA) circuit based on this opamp is presented to test the feasibility of a reconfigurable pipeline ADC. Simulations using STMicroelectronics 45-nm device models show that the opamp gain remains quite constant up to a supply voltage of 0.5V, and the amplifier can still be used with a supply as low as 0.3V. The SHA maximum sampling frequency decreases with supply voltage, and good performance with low power consumption is achieved.


Enhanced Differential Super Class-AB OTA

M. Garde1, A. Lopez-Martin1, J. Ramirez-Angulo2

1Public University of Navarra, Spain; 2New Mexico State University, United States

A fully differential Super Class AB Operational Transconductance Amplifier (OTA) is presented. It is based on the combination of adaptive biasing techniques for the differential input stage and Local Common Feedback (LCMFB) which provides additional dynamic current boosting and increased gain- bandwidth product (GBW). Additionally, Quasi Floating Gate (QFG) transistors have been used, enhancing the performance of the amplifier. The OTA has been fabricated in a standard 0.5μm CMOS process. Simulation results show a greatly improved slew rate by factor 86 and gain-bandwidth product increase by factor 16 when compared to the class A OTA while driving the same 70pF load. The circuits are operated at +/-1V supply voltages with only 10μA quiescent current. The overhead in terms of area, noise, and static power consumption, is minimal.

16:40-18:10 COMPETITION Session I
Room #4 - Plenary room
 Chair: Prof. R. Castro Lopez, Instituto de Microelectronica de Sevilla, IMSE-CNM, CSIC, Universidad de Sevilla, Spain

Low-cost acquisition method for on-line inductor characterization in switched power converters

Matteo Lodi, Alberto Oliveri and Marco Storace

University of Genoa, Italy

This paper presents a low-cost method for on-line monitoring the inductor behavior in a switch-mode power converter. The method exploits the embedded electronics already available for the converter control, typically a microcontroller. By properly sampling the inductor voltage and current, the method allows estimating on-line the inductor’s ripple and mean current, power-consumption and inductance, which is of great practical importance when ferrite-core inductors are employed in partial saturation. The method is validated on a boost converter.


A New Method for the Analysis of Movement Dependent Parasitics in Full Custom Designed MEMS Sensors

Axel Hald1, Johannes Seelhorst1, Pekka Herzogenrath1, Jurgen Scheible2 and Jens Lienig3

1Automotive Electronics, Robert Bosch GmbH, Germany; 2Reutlingen University, Germany; 3Dresden University, Germany

Due to the lack of sophisticated microelectromechanical systems (MEMS) component libraries, highly optimized MEMS sensors are currently designed using a polygon driven design flow. The strength of this design flow is the accurate mechanical simulation of the polygons by finite element (FE) modal analysis. The result of the FE-modal analysis is included in the system model together with the data of the (mechanical) static electrostatic analysis. However, the system model lacks the dynamic parasitic electrostatic effects, arising from the electric coupling between the wiring and the moving structures. In order to include these effects in the system model, we present a method which enables the quasi dynamic parasitic extraction with respect to in-plane movements of the sensor structures. The method is embedded in the polygon driven MEMS design flow using standard EDA tools. In order to take the influences of the fabrication process into account, such as etching process variations, the method combines the FE-modal analysis and the fabrication process simulation data. This enables the analysis of dynamic changing electrostatic parasitic effects with respect to movements of the mechanical structures. Additionally, the result can be included into the system model allowing the simulation of positive feedback of the electrostatic parasitic effects to the mechanical structures.


Automated Generation of System-Level AMS Operating Condition Checks: Your Model's Insurance Policy

Georg Glaser1, Martin Grabmann1, Gerrit Kropp1 and Andreas Furtig2

1Insitut fur Mikroelektronik und Mechatronik Systeme gemeinnutzige GmbH, Germany; 2Institute for Computer Science, Goethe Universitat Frankfurt a. M., Germany

Analog/Mixed-Signal (AMS) design and verification strongly relies on more or less abstract models to make extensive simulations feasible. Maintaining consistent behavior between system model and implementation is crucial for a correct verification. Operating conditions have to be a major concern: A faulty model might introduce false-positive verification results despite of erroneous operating conditions. We propose a novel method to automatically generate a model safe-guard unit from transistor-level simulation data. We introduce this unit into an abstract model in VerilogAMS to check the validity of the current operating conditions. This method can be used to significantly reduce the risk of erroneous verification results on system level. We demonstrate our approach using an RFID emdodulator circuit. The model is automatically augmented with additional checks derived from an exploration of the underlying circuits' parameter space. By comparing the risk of false-positive simulation results, we prove that the design risk can be nearly eliminated.

Wednesday, June 14th
10:20-12:00 Emerging and Non-CMOS Technologies II
Room #1 - VULCANO
 Chair: Dr. A. Gola, ON Semiconductors, Czech Republic

Inkjet-Printed Patch Antennas for Wireless Chip-to-Chip Communication on Flexible Substrates

Q. Hirmer1, A. Albrecht1, M. Bobinger1, M. Loch1, M. Haider1, J. Russer1, M. Becherer1, P. Lugli2

1TU Munich, Germany; 2Free University of Bozen-Bolzano, Italy

Printed electronics become more and more relevant for applications in wearable electronics and sensors. Inkjet printing of silver nano-particles can be done at very low cost with a reasonably high precision and conductivity. In this paper, we investigate flexible patch antennas for wireless chip-to-chip communication scenarios, rapidly prototyped using an inkjet printing process. A patch antenna with a return loss of almost -20 dB at a resonance frequency of 2.09 GHz that agrees well with the conducted simulations is presented.


A Virtual III-V Tunnel FET Technology Platform for Ultra-Low Voltage Comparators and Level Shifters

F. Settino1, M. Lanuzza1, S. Strangio2, F. Crupi1, P. Palestri3, D. Esseni3

1University of Calabria, Italy; 2LFoundry, Italy; 3University of Udine, Italy

In this paper, a III-V nanowire TFET technology platform is compared against the predictive technology models of FinFETs at 10 nm node by evaluating the performance of two different comparator topologies. Furthermore, the potential of a hybrid FinFET/TFET approach in multi supply voltage design is addressed by considering level shifter circuits. Both analyses confirm that III-V TFET represents a promising technology option for future integrated circuits with sub-0.4 V operation.


3D Printed Capacitive Sensor with Corrugated Surface

A. Tuna1, O. Erden1, Y. Gokdel1, B. Sarioglu1

1Istanbul Bilgi University, Turkey

In this work, a novel 3D printed capacitive pressure sensor with a corrugated surface is presented. The design composed of top and bottom plates. The sensor is 3D printed using a commercially available polymer material and then coated with Cr and Au with the sputtering process. The dimensions of produced structure that designed are 11x11x4.6mm^3. Due to the corrugated surface, the area of the plates is increased 19.46% compared to a standard flat surface parallel plate capacitive sensor in the same bulk area. The design process of the sensor, simulation and the experimental results are given and explained in detail. The performance of the sensor is tested with various pressure levels between 0 Pa and 8.88 kPa. The experimental results show that the capacitance range of the sensor is 2.7 pF-4.3 pF. The maximum sensitivity of the sensor is obtained as 0.14 pF/kPa. The results confirm that the presented capacitive sensor can be utilized for carrying out pressure measurements.


Design Approach of a Large Strain Sensor Based on Nanoparticle Technology

S. Ameduri1, M. Ciminello1, A. Concilio1, A. Brindisi1, L. Mazzola1, F. Piscitelli1, R. Volponi1, O. Petrella1, R. Sorrentino1, B. Tiseo1

1Centro Italiano Ricerche Aerospaziali, Italy

The work at hand illustrates the design approach adopted for a large strain sensor, based on the carbon nanotube (CNT) technology, devoted to operations of structural health monitoring and shape reconstruction. After a critical discussion on the specifications, the most suited materials and processes were selected, with specific focus on the dispersion and deposition strategies. Then, by means of a FE approach, the topology in terms of CNT volume concentration, morphology (curvature) and orientation, was identified. A feasibility study on the manufacturability was then carried out. Finally, in compliance with the initial specifications, the set of calibration and space qualification tests was illustrated. The above mentioned activities were developed within the Project "Graphene-Polymeric Spray Sensor for Shape Recognition of Super-Deformable Structures", GRAPSS, sponsored by CIRA within the "Curiosity Driven" initiative.


High-Performance X-Band LNAs Using a 0.25-um GaN Technology

M. Vittori1, S. Colangeli1, W. Ciccognani1, A. Salvucci1, G. Polli1, E. Limiti1

1University of Roma "Tor Vergata", Italy

This work presents two LNAs, LNA A and LNA B: respectively operating in the 8-10 GHz band and 10-12 GHz band; together they cover the full X-band. The power consumption results very low and it is equal to 0.9 W for each amplifier. The total area for each LNA is 3.0x1.5 mm2. A very low noise figure has been achieved, namely of 1.1 dB (LNA A) and 1.3 dB (LNA B). The peak gain is 27 dB (LNA A) and 25 dB (LNA B). The obtained results mark an increase in performance for the 0.25 um GaN technology in terms of noise figure, gain and matching, improving the current state of the art of GaN-based LNAs.

10:20-12:00 Sensing Systems II
Room #2 - PANAREA
 Chair: Prof. G. Ferri, University of L'Aquila, Italy

Compact Millimeter Wave Architecture Dedicated to Object Detection Using Dual-Band/Dual-Polarization and Impulse Method

P. Diao1, T. Alves1, B. Poussot1, M. Villegas1

1University of Paris Est, France

A dual band - dual polarization system is proposed to improve detection performances in terms of continuous detection. The dedicated architecture uses impulse mode with differential structure. For improving detection range, cumulative detection is used. Results from simulations are presented for metallic cylinder in comparison with conventional single - band detection system.


Sensing Road Pavement Health Status through Acoustic Signals Analysis

R. Fedele1, F. Della Corte1, R. Carotenuto1, F. Pratico1

1University of Reggio Calabria, Italy

Traffic produces seismic and acoustic waves. These waves affect both bystanders and civil infrastructures in terms of health issues and of complication in the maintenance, rehabilitation, assessment and monitoring processes, respectively. Therefore, it is more and more necessary to reduce, or at least to monitor these annoyances through methods that are capable to take advantage of the potentialities offered from new technologies. The aim of this study is to present the preliminary results of the application of a new method for the monitoring the traffic-induced vibrations and noise, and for the assessment of the health conditions of road pavements. This method can be classified as an acoustic method because it is based on the concept of acoustic signature, defined in this work as the spectral content of the acoustic signals coming from the road pavement under vehicular traffic condition. The estimation of variation over time of this signature provides important information about the changes of the response of roads to the traffic, i.e. about their structural health conditions. In this preliminary stage, acoustic signals were detected through a sensor placed in a hole drilled both in un-cracked and cracked slabs of asphalt concrete, during accelerated loading in-lab tests (EN 12697-22:2007). Simultaneously, these signals were sampled and processed in order to carry out the acoustic signature of the slab under test. Results show the possibility of developing a new acoustic method that allows estimating the structural health condition of a road pavement from its acoustic signature.


Improved Event-Driven Touch CMOS Sensor

A. Abou Khalil1, M. Valle2, H. Chible3, C. Bartolozzi1

1Istituto Italiano di Tecnologia, Italy; 2University of Genova, Italy; 3Lebanese University, Lebanon

In this paper, we present a new version of previously fabricated event driven tactile sensor [1] with modifications across its circuits and methods involved using the AMS CMOS 0.18um technology. Electrical characterization experimental results are shown and compared to the ones from the previous proving the advantages of the new sensor concerning area saving, sensing small input signals and power consumption.


Proposal for a New ALICE-PHOS, CPV Front-End Electronics Topology

C. Seguna1, E. Gatt1

1University of Malta, Malta

This paper presents the proposal of a new front-end readout electronics architecture for the ALICE Charged-particle Veto detector (CPV) module located in PHOton Spectrometer (PHOS). With the upgrades in hardware typology and proposed new readout scheme in FPGA design, the CPV shall achieve at least five times the readout speed of the present front-end readout electronics. Design choices such as using the ALTERA Cyclone V GX FPGA, the topology for parallel readout of Dilogic cards and an upgrade in FPGA design interfaces will enable CPV to reach an approximate interaction rate of 50 KHz. This paper presents the new system hardware as well as the preliminary prototype measurement results. This paper concludes with recommendations for other future planned updates in hardware schema.


RSSI Overboard Localization System for Safe Evacuation of Large Passengers Ships

N. El Agroudy1, G. Georgiades2, N. Joram1, F. Ellinger1

1TU Dresden, Germany; 2GGDedalos Technology Services, Cyprus

This work presents an overboard localization system based on measuring the received signal strength indicator (RSSI) between smart lifejacket tags and one interrogator station mounted inside an unmanned aerial vehicle (UAV). Localization is based on weighted least mean squares (LMS) algorithm. Simulations that study the effect of the UAV search path on the localization accuracy are presented and it shows that the parallel tracks search path gives better localization results compared to other search paths. Measurements are carried out in a search area of 500 m x 350 m, where tags are localized with a mean error of 37.5 m. The measurement results show better localization accuracy compared to other RSSI based localization algorithms.

10:20-12:00 Radio Frequency Circuits and Systems II
Room #3 - LIPARI
 Chair: Prof. C. Dehollain, Ecole Polytechnique Federale de Lausanne, Switzerland

Compact Monolithic Spiral Quadrature Coupler Design

F. Tabarani1, H. Schumacher1

1University of Ulm, Germany

The design and performance of two compact monolithic spiral quadrature couplers are presented, employing a novel configuration of mutually coupled coils. The first, designed at 20.35 GHz, occupies 131 x 142 μm and achieves 0.5 dB fractional bandwidth of 19%, with phase error and intrinsic loss below 2.6° and 0.92 dB, respectively. The second, designed at 30.15 GHz with 5.24 dB coupling coefficient, measures 122 x 132 μm and achieves 0.5 dB fractional bandwidth of 30% with a phase difference between 93 and 103°. The insertion loss is smaller than 0.93 dB.


A 230.5-238.8-GHz Magnetically Coupled Triple-Push Oscillator with Inductive Tuning for Data Transmission in 45-nm CMOS

U. Celik1, W. Steyaert1, P. Reynaert1

1KU Leuven, Belgium

A scalable coupled triple-push voltage-controlled oscillator (VCO) based on inductor switching is analyzed and proposed for data transmission via binary frequency shift keying (BFSK) at sub-terahertz (THz) frequencies in 45nm predictive CMOS bulk technology. Inductive switching enables better quality factors above 100GHz due to the increasing losses associated with capacitors. Novel inductor switching technique is proposed in order to enable easy coupling and wide tuning range at the same time for data transmission above 200GHz. Simulation results suggests that 12.3Gbps data rate is possible to be achieved. -12.4dBm output power is achieved with only a variation of 0.2dB in 7.4GHz bandwidth. Oscillation frequency can be tuned from 224GHz to 231.4GHz for single core VCO. Power consumption is 15.5mW for one core. The proposed oscillator is easy to magnetically couple from gate inductors to generate higher output powers depending on the transmission distance and losses. Two coupled VCO is implemented as a proof of concept and reaches up to -10.5dBm output power with a bandwidth of 8.25GHz. To the authors' knowledge, this is the first VCO above 200GHz that uses inductor switching and BFSK.


Ka Band Passive Differential 4:1 Power Divider/Combiner Based on Wilkinson Topology

M. Balducci1, H. Schumacher1

1University of Ulm, Germany

The design and characterization of a K and Ka differential four ways power divider/combiner based on Wilkinson like topology, implemented in a 0.25 um SiGe BiCMOS technology is presented in this paper. The wide band device presents a transmission coefficient better than -8.6 dB, a 2.6 dB additional loss over the ideal case. The input/output reflection coefficient is better than -10dB and the isolation between output ports is better than -10dB, in the frequency range 20 GHz - 38 GHz. The use of a differential design is very attractive for transmit/receive modules in satellite communication applications when the assembly use bondwires interconnects. In this scenario, the use of a differential power divider instead of a single ended version permits to decrease the losses in the multifunctional monolithic microwave ICs, i.e. the power and the area consumption.


A Low-Noise K-Band Class-C VCO for E-Band 5G Backhaul Systems in 65-nm BiCMOS Technology

N. Lacaita1, M. Bassi1, A. Mazzanti1, F. Svelto1

1University of Pavia, Italy

Next-generation 5G communication systems require adaptive high-order modulations to increase spectral efficiency. To limit EVM, very low phase noise levels are required - i.e. less than -117dBc/Hz at 1MHz offset for 64QAM at f=20GHz. In this paper, the design and measurements of a low-noise K-Band VCO are presented. The challenges of achieving such a low phase noise are discussed in detail, with particular emphasis on the minimization of L/Q, inductor versus quality factor ratio. Prototypes have been realized in a 55nm BiCMOS technology. Operated at 2.5V supply with the largest amplitude allowed by reliability constraints, measurements show a phase noise as low as -119dBc/Hz at 1MHz from a 20GHz carrier offset with a tuning range (TR) of 19% and FoM=-187dBc/Hz. Power consumption is 56mW. To the best of authors' knowledge, the presented VCO shows the lowest reported phase noise among state-of-the-art BiCMOS VCOs with TR>10%.


Layout Considerations for Common-Base Amplifiers Operating at 200 GHz

P. Testa1, S. Li1, C. Carta1, F. Ellinger1

1TU Dresden, Germany

This paper presents layout-considerations for common-base amplifiers operating in the deep millimeter-wave region around 200 GHz. The effects of the parasitics for different layouts have been investigated, searching for the optimal performance in terms of gain and bandwidth of operation. Different layouts have been tested with the fabrication of two commonbase amplifiers. The employed fabrication process is a 0.13 um SiGe BiCMOS technology with max oscillation frequency (fmax) of 450 GHz. The fabricated devices have been embedded into a balanced architecture, which guaranteed input and output matching, and high stability of the amplifier. The two designs had different values of parasitic inductance for the base-connection of the transistors. The engineered parasitics of the first design boosted the gain up to 27 dB and 23 dB at 160 GHz and 210 GHz, respectively; while the second design optimized for minimal parasitics showed a very broadband of operation ranging from 155 GHz to 215 GHz. Compared against the state of the art of SiGe common-base amplifiers operating at millimeter-waves, the presented layout considerations enabled the highest reported gain-bandwidth product.

10:20-12:00 Circuit simulation and synthesis
Room #4 - Plenary room
 Chair: Prof. M. Berke Yelten, Istanbul Technical University, Turkey

Inversion Coefficient Optimization Assisted Analog Circuit Sizing Tool

Engin Afacan and Gunhan Dundar

Bogazici University, Turkey

Many analog circuit synthesis tools have emerged over the last two decades in order to combat increased design complexity and reduce the design time. However, the efficiency of these tools (time performance) is still a problem, where solving of a highly nonlinear design problem takes relatively long time even if the process is fully automated. Considering conventional analog circuit design, selection the operating point is essential to achieve a better performance, where inversion coefficient (IC) is commonly utilized as a sizing and biasing independent design parameter, which spans the entire range of saturation region (weak, moderate, strong inversion), and provides a valuable guidance to designer during the design process. Currently, analog circuit sizing tools utilize simplified equations to determine the transistor operating region, where all transistors are forced into the saturation region. Even if all transistors are kept in saturation, the inversion type of transistors has not been taken into account. In this study, a novel analog circuit sizing tool is presented, which facilities the sizing process by optimization of IC to enhance the time to converge.


New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing Optimization

Nuno Lourenco1,2, Ricardo Miguel Martins1,2, Ricardo Povoa1,2, Antonio Canelas1,2, Nuno Horta1,2, F. Passos3, R. Castro-Lopez3, E. Roca3 and F.V. Fernandez3

1Instituto de Telecomunicacoes, Lisbon, Portugal; 2Instituto Superior Tecnico, Lisbon, Portugal; 3Instituto de Microelectronica de Sevilla, IMSE-CNM, CSIC and Universidad de Sevilla, Spain

This paper presents new indexing and mutation operators, in the context of bottom-up hierarchical multi-objective optimization of radio frequency integrated circuits, for pre-optimized sets of solutions from the hierarchical sub-levels when moving up in hierarchy. Two ideas, one based on a Voronoi decomposition and another based on the nearest neighborhood, are explored, where, and unlike previous approaches that are based on sorting, the distance between elements determines the probability of decisions taken during optimization. Three implementations of those ideas were tried in AIDA’s NSGAII evolutionary kernel, and successfully used in the optimization of a Voltage Controlled Oscillator and a Low Noise Amplifier with pre-optimized inductor sets obtained using the SIDeO toolbox, showing their strengths when compared to previous state-of-the-art mapping strategies.


Developing a Web-based Symbolic Circuit Analysis Tool for Learning and Design Aid

Hao Yu and Guoyong Shi

Shanghai Jiao Tong University, China

Internet-based computing is booming. This has brought positive effects on education and engineering design practice. This paper introduces the development details on a web-based symbolic circuit simulation tool AICE (Analog IC Explorer). Unlike SPICE simulators, symbolic tools are small and compact. Making a symbolic tool available online as a web service has many benefits: 1) cross-platform, 2) wide and easy accessability, 3) friendly interaction and easy documentation, and 4) collaborative learning and design aid. The proposed web based symbolic analysis tool for analog IC design contains a schematic editor, a symbolic function generator, file managing system, and user account manager, etc. The currently popular development platform and tools are introduced. A running service is demonstrated by examples.


Real-Time Emulation of Block-Based Analog Circuits on an FPGA

Philipp Tertel and Lars Hedrich

University of Frankfurt, Germany

In order to provide a real-time emulation platform for analog signal processing circuits, we propose a block based approach with a constant worst case runtime. We evaluate an FPGA-based implementation of this approach by comparing its output for different test cases to a non-real-time SPICE simulation. The implementation runs at a sampling rate of 88.2 kHz and features roundtrip times as low as 0.096 ms (12 bit ADC) and 0.190 ms (16 bit ADC). For complex filter structures we were able to replicate the frequency responses predicted by a SPICE AC analysis accurately. Furthermore we compare measured transient responses of the FPGA-based emulation with SPICE and discuss advantages and disadvantages of the approach.


Simulation of Broadband Transient Signals in Frequency-Domain using Impedance Parameters

Florian Protze, David Ihle, Martin Kreißig, Udo Jorges and Frank Ellinger

Technische Universitat Dresden, Germany

In order to design and simulate broadband communication systems like Ethernet, accurate models up to 375 MHz and efficient simulations are necessary. This paper provides an approach to model analog two-port systems using impedance parameters purely in the digital domain. The twisted-pair copper line is modelled based on frequency dependent impedance parameters gained from FEM (finite element method) field solver software. The necessary steps to use the impedance parameters for frequency-domain (FD) simulation of transient signals are given. A way to simulate very long input signals using the overlap-add method is shown. Two examples for simulating broadband transient signals using this approach show the utility.

13:00-14:40 Modeling, Optimization, and Characterization II
Room #1 - VULCANO
 Chair: Prof. N. Horta, University of Lisbon, Portugal

Dynamic Stability of a Closed-Loop Gate Driver Enabling Digitally Controlled Slope Shaping

J. Groeger1, K. Norling2, B. Wicht1

1Robert Bosch Center for Power Electronics, Germany; 2Infineon Technologies, Austria

A concept for a slope shaping gate driver IC is proposed, used to establish control over the slew rates of current and voltage during the turn-on and turn-off switching transients. It combines the high speed and linearity of a fully-integrated closed-loop analog gate driver, which is able to perform real-time regulation, with the advantages of digital control, like flexibility and parameter independency, operating in a predictive cycle-by-cycle regulation. In this work, the analog gate drive integrated circuit is partitioned into functional blocks and modeled in the small-signal domain, which also includes the non-linearity of parameters. An analytical stability analysis has been performed in order to ensure full functionality of the system controlling a modern generation IGBT and a superjunction MOSFET. Major parameters of influence, such as gate resistor and summing node capacitance, are investigated to achieve stable control. The large-signal behavior, investigated by simulations of a transistor level design, verifies the correct operation of the circuit. Hence, the gate driver can be designed for robust operation.


Investigation on the Demodulation of Multi-Tone Interference in Feedback OpAmps

M. Brignone Aimonetto1, F. Fiori1

1Politecnico di Torino, Italy

In this paper the effect of multi-tone interference on feedback Operational Amplifiers is explored since the continuous wave approach do not describe actual disturbance. Under the assumption of weak non-linearity, an analytical model is derived to predict the offset caused by the superposition of an arbitrary number of sinusoidal interference applied to the input of a feedback amplifier. Moreover it can be used to evaluate of the intermodulation distortion caused by a two-tone interference. The validity of the approach is validated through computer simulations.


Nonlinear Modeling of Cross-Coupled Regenerative Sampling Oscillators

H. Ghaleb1, M. El-Shennawy1, U. Joerges1, C. Carta1, F. Ellinger1

1TU Dresden, Germany

This paper presents two approaches to model the startup behavior of cross-coupled oscillators for regenerative sampling applications. The first approach closely models the building blocks and connections of the circuit at the device level, whereas the second approach uses an equivalent model based on the analysis of the differential currents in the circuit to simplify the calculation and obtain a faster solution. The models have been implemented using standard components from the "analogLib" and "ahdlLib" libraries in the CADENCE design environment, which provides access to familiar powerful tools and simulation setups. Thus, the design time is significantly reduced. The model is extended with an ideal mixer and the results are verified with the down-converted output of a fabricated 145-GHz regenerative oscillator. This work facilitates the study of the startup behavior of oscillators for a wide range of applications without the need for complex mathematical analysis.


A TCAD Modeling Approach for Diamond Particle Detectors: Simulation and Test

A. Morozzi1, D. Passeri1

1University of Perugia and INFN Perugia, Italy

In order to fully exploit the properties of diamond in electronic semiconductor applications, standard design and verification tools should be adopted, following the conventional TCAD design flow. However, diamond is not included in the material's library of commercial TCAD simulation tools, due to the novelty of using this material in electronics. To this end the TCAD tools capabilities have been enhanced by developing an innovative numerical model for the simulations of advanced diamond devices conceived for particle detection in High-Energy Physics (HEP) experiments. This work focuses on the parameterization of the TCAD numerical model for polycrystalline diamond, on its validation against experimental data and on its application as a predictive tool for the electrical behavior of commercial polycrystalline diamond and Diamond-on-Iridium detectors.


Fractional-N PLL Phase Noise Effects on Baseband Signal-to-Noise Ratio in FMCW Radars

M. El-Shennawy1, B. Qudsi1, N. Joram1, F. Ellinger1

1TU Dresden, Germany

This work presents a model for estimating the effect of the fractional-N phase locked loop (Frac-N PLL) phase noise (PN) on frequency modulated continuous wave (FMCW) radar baseband (BB) signal-to-noise ratio (SNR). The model captures the SNR degradation due to PN in secondary radars and as well as the range correlation effect in primary radars which reduces the amount of SNR degradation. Estimates from the proposed model are in good agreement with measurement results from a dual band FMCW radar test chip fabricated on an IBM7WL BiCMOS 0.18 μm technology. In secondary radar mode, a BB SNR of 30.0 and 23.0 dB is achieved at the 2.4 and 5.8 GHz bands respectively while in primary radar mode a BB SNR of 35.0 and 33.7 dB is achieved at the same bands. The fabricated FMCW radar test chips achieved a ranging precision of 5.2 and 0.3 mm in secondary and primary radar modes respectively.

13:00-14:40 Emerging devices
Room #2 - PANAREA
 Chair: Prof. I. Ercan, Bogazici University, Turkey

Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework

Raffaele De Rose1, Greta Carangelo1, Marco Lanuzza1, Felice Crupi1, Giovanni Finocchio2 and Mario Carpentieri3

1DIMES, University of Calabria, Italy; 2MIFT-University of Messina, Italy; 3DEI, Polytechnic University of Bari, Italy

In this paper, we focus on the study of the impact of voltage scaling on writing performance and energy of STT-MRAM arrays featuring four different configurations of bitcell. The memory arrays are implemented by a circular MTJ with a diameter of 30 nm and a 28-nm UTBB FDSOI CMOS technology. The analysis is performed by considering the effect of both CMOS and MTJ process variations, and the stochastic variations of the MTJ switching time. The MTJ behavior is integrated into a commercial circuit design tool in the form of a Verilog-A LUT-based code, which exploits as inputs the outcomes of micromagnetic multi-domain simulations to ensure more accurate modeling of the MTJ characteristics. Simulation results show that the write performance and energy of STT-MRAMs strongly depend on the bitcell configuration. The energy saving achieved through voltage scaling is found to be up to 37% at the cost of a delay penalty of 3.3X, as compared to the write operation at the nominal voltage of 1 V.


Modified MIM Model of Titanium Dioxide Memristor for Reliable Simulations in SPICE

Dalibor Biolek1,2, Viera Biolkova2 and Zdenek Kolka2

1University of Defence, Brno, Czech Republic; 2Brno University of Technology, Brno, Czech Republic

Modifications of the mathematical model of the TiO2 memristor, based on the approximations of Simmons’ equations of tunnel effects in Metal-Insulator-Metal structures, are proposed. These modifications improve the performance of the model in the SPICE environment, taking into account the numerical limits of SPICE-family programs.


Spin-Torque Memristor based An Offset Cancellation Technique for Sense Amplifiers

Mesut Atasoyu1, Mustafa Altun1, Serdar Ozoguz1 and Kaushik Roy2

1Istanbul Technical University, Turkey; 2Purdue University, USA

In this study, we propose an offset cancellation technique with the spin-torque memristors where are unpredictable threshold voltage changes of transistors that results in the input referred random offset (IRRO) of amplifiers. Motivated by this fact, this study focuses on the IRRO cancellation in sense amplifiers with the aid of the spin-torque memristor technology. The spin-torque memristors in series perform less resistance and process variations from parallel connection. The resistance value of the spin-torque memristor was regarded as frozen when the current flow over the spin-torque memristor is lower than its critical switching current value. In fact, the proposed structure employs a non-destructive sensing scheme in order to achieve a relatively large sense margin by reducing the IRRO. Our main idea is to reduce or eliminate the IRRO exploiting the spin-torque memristors for providing the current matching on the input transistors of the voltage comparator. In particular, the overwrite problem of the spin-torque memristor was solved by setting the critical switching current of the spin-torque memristor to be greater than a current value corresponding to maximum the IRRO value. We evaluated the IRRO cancellation technique on the proposed comparator or sense amplifier using 45nm predictive CMOS technology. Although sense amplifiers are targeted in this study, our technique can be applied to any analog amplifier suffering from the IRRO.


Synthesis and Fundamental Energy Analysis of Fault-Tolerant CMOS Circuits

Ilke Ercan1, Omercan Susam2, Mustafa Altun2 and M. Husrev Cilasun3

1Bogazici University, Turkey; 2Istanbul Technical University, Turkey; 3Aselsan, Turkey

In this study, we perform a physical-information- theoretic analysis to obtain fundamental energy dissipation bounds for fault-tolerant reversible CMOS circuits we synthesize using Hamming codes. We show that the approach we had initially developed to calculate theoretical efficiency limitations of emerging electronic paradigms can also be applied to CMOS technology base and can provide feedback to improve circuit design and performance. We illustrate our physical-information- theoretic methodology via applications to circuits that we synthesized using Hamming codes that result in detection of up to (d-1) bit errors and correction of up to (d-1)/2 bit errors where d represents the minimum Hamming distance between any pair of bit patterns. The fundamental lower bounds on energy dissipation are calculated for a one-bit reversible full adder and for irreversible full adders with block-code-, dual modular redundancy (DMR)- and triple modular redundancy (TMR)-based CMOS circuits. Our results reflect the fundamental difference in energy limitations across these circuits and provide insights into improved design strategies.


Towards a Nanofabricated Vacuum Cold-Emitting Triode

Davide Patti1, Salvatore Pennisi2, Salvatore Lombardo3 and Giuseppe Nicotra3

1STMicroelectronics, Italy; 2DIEEI, University of Catania, Italy; 3CNR, IMM, Italy

A technique to fabricate a vacuum cold-cathode nanoelectronic diode with a remarkably low 2-V turn-on voltage was recently presented. A three-terminal device based on the same technology is here designed and fabricated, to implement a vacuum nano-triode. The attempt was partially successful as the excessively large gate radius does not allow effective current control. Nonetheless, the obtained experimental results still disclose fundamental behaviors improving both the art and knowledge in the field. Specifically, it is found that: 1) thermionic field emission is ascertained both from a metal tip and from a silicon tip with a nearly 2-V turn-on voltage; 2) the gate current is negligible and the cathode current is efficiently collected by the anode, 3) emission is quite insensitive to temperature and the device can work also at high temperatures, observed up to 300°C in a reliable manner. Finally, the unexpected bidirectional conduction can open a new scenario for the implementation of triac-like vacuum nanodevices.

13:00-15:00 RF, sensors and MEMS
Room #3 - LIPARI
 Chair: Prof. Javier Sieiro, Universitat de Barcelona, Spain

Extending the Frequency Range of Quasi-Static Electromagnetic Solvers

Saiyd Ahyoune1, Javier Sieiro1, Tomas Carrasco1, Neus Vidal1, Jose M. Lopez-Villegas1, Elisenda Roca2 and Francisco V. Fernandez2

1Universitat de Barcelona, Spain; 2Instituto de Microelectronica de Sevilla, CNM-CSIC, Universidad de Sevilla, Spain

In this work, a combination of 2D and 3D quasi-static Green's functions (GF) is proposed for extending the frequency range validity of the quasi-static approximation. It is shown that 3D-GF is very accurate at low frequency, whereas 2D-GF is more suitable at higher frequencies because it is the actual solution of the transverse electromagnetic (TEM) propagation mode. The mixing of both GFs is controlled through the ratio of the main size of the device versus the wavelength at the given simulation frequency. Numerical examples are compared with experimental data for different passives in a broadband frequency range.


Design of a LTE-Receiver Using a Design Methodology for Multiphysical RF Systems

Jacek Nowak, Dominik Krauße, Mahmoud Mona, Ralf Sommer and Johannes Stegner

TU Ilmenau, Germany

This paper deals with the design of a receiver for LTE band 20 consisting of microelectronic and MEMS-containing function blocks. It shows how multiphysical RF circuits can be considered in one design environment like Cadence Virtuoso. Finally, the simulation tool was extended by suitable models for used MEMS containing design parameters that are important for an electronics engineer. This unifies the design task and facilitates the evaluation of an implementation with and without MEMS by considering the entire receiver chain.


LNA-ESD-PCB Codesign for Robust Operation of IR-UWB Non-coherent Receiver

Okan Zafer Batur1, Gunhan Dundar2 and Mutlu Koca2

1Istanbul Bilgi University, Turkey; 2Bogazici University, Turkey

In this paper, we present a radio frequency (RF) front-end design for increasing robustness of non-coherent energy detection based impulse radio (IR) ultra-wideband (UWB) receivers in impulsive noise environment. Robustness against impulsive noise is achieved by on chip LNA-bandpass filter (BPF) circuit, which also works as a clipper for high energy impulsive noise bursts. The electrostatic discharge (ESD), wirebond, pad capacitance, and the chip package model are co-designed with wideband cascode LNA structure. These unwanted capacitive and inductive elements are designed as a part of input BPF. The LNA output stage includes an inductor that is coupling with the input capacitance of the VGA block results in additional filtering. In the post-layout simulations, 45 dB impulsive noise compression has been achieved. It has been shown that the RF front-end and LNA output stage reduces the impulsive noise and increases the noise performance of the IR-UWB receiver, hence becoming robust against the impulsive noise.


A New Robustness Optimization Methodology for MEMS-IC Systems

Florin Burcea, Andreas Herrmann, Aditya Gupta and Helmut Graeb

Technical University of Munich, Germany

MEMS based sensor circuits are traditionally designed separately using CAD tools specific to each energy domain (mechanical and electrical). This paper presents a new approach for the robustness optimization of a MEMS-IC system. The new methodology is exemplified for a MEMS microphone with readout circuit. The design parameters of both the MEMS and the IC part are subject to optimization. Advanced methods for robustness analysis and optimization in consideration of operating and process parameters, developed for ICs, are transferred to MEMS based sensor circuits. The optimization succeeds only when considering both mechanical and electrical parameters. To save CPU time, a reduced-order model is used for the MEMS part. To integrate the generation of the simplified model into the optimization flow, a new simulation-in-a-loop flow based on commercial tools is implemented.


Compact Model Based Design Space Exploration for CMOS Hall Effect Sensors

Ibrahim Aksoyak, Kaan Balaban, Hamdi Torun and Gunhan Dundar

Bogazici University, Turkey

The paper presents an analytical model for Hall Plates. The model includes the calculation of some key features such as Hall voltage, resolution, sensitivity, and signal-to-noise ratio (SNR) for different device geometries. The model is used to determine the device geometries for the best optimization parameters in the design of Hall plates. The model is validated with the measurements taken from a Hall Plate.


Comprehensive Detection of Counterfeit ICs Via On-Chip Sensor and Post-Fabrication Authentication Policy

Yaoyao Ye1, Taeyoung Kim2, Haibao Chen1, Hai Wang3, Esteban Tlelo-Cuautle4 and Sheldon X.-D. Tan2

1Department of Micro/Nano Electronics, Shanghai Jiao Tong University, Shanghai, China; 2Department of Electrical and Computer Engineering, University of California, Riverside, CA, USA; 3School of Microelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu, China; 4Department of Electronics, INAOE, Mexico

Counterfeit integrated circuits (ICs) have posed a major security and safety threat on commercial and mission-critical systems. In this paper, we propose to develop a comprehensive counterfeit ICs detection and prevention strategy, consisting of an innovative multi-functional on-chip sensor and a related post-fabrication authentication methodology. We target at many counterfeit ICs including the recycled/remarked/out-ofspec ICs, as well as cloned and over-produced ICs. First, the new sensor consists of antifuse memory and aging sensors to reduce reference circuit related area overhead of those sensor circuits. Second, the new sensor combines both the ring-oscillator based aging sensor with recently proposed electromigration(EM)-based aging sensor so that it can be effective for estimation of both short and long period time of chip usage. Third, on top of the new sensor, we propose a new post-fabrication authentication methodology to detect and prevent non-defective counterfeit ICs. Simulation results show the advantage of the proposed multi-functional sensor against existing on-chip sensors in terms of functionality, detection coverage and usage time estimation range and accuracy.

13:00-15:00 Reliability and Resiliency
Room #4 - Plenary room
 Chair: Prof. G. Dundar, Bogazici University, Turkey

1-GRad TID Impact on 28-nm HEP Analog Circuits

F. Resta1, S. Gerardin2, S. Mattiazzo2, A. Paccagnella2, M. De Matteis1, C. Enz3, A. Baschirotto1

1University of Milano Bicocca and INFN Milano Bicocca, Italy; 2University of Padova, Italy; 3EPFL, Switzerland

The Total Ionizing Dose (TID) levels foreseen after the future upgrade of the CERN Large Hadron Collider (High Luminosity LHC) will heavily influence the performance of the electronics. A TID level of 1GigaRad will be accumulated in the innermost layer of the pixel detector in 10 years of operations, which could damage the readout circuits behavior with important failures in the experiments. To prevent this situation, the choice of a proper technology for the readout ASICs represents a key point. This paper deals with the characterization of single transistors and of an analog circuit, both realized in a TSMC 28nm bulk CMOS technology, after being irradiated with 1 GigaRad TID. nMOS devices result more resistant than pMOS showing a weak degradation of the electrical parameters. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as that hereby presented. In the proposed analog circuit, the high radiation level induces a 20% gain reduction and an 80% slowdown of the Charge Sensitive Preamplifier time response.


Self-Heating Effects on the Thermal Noise of Deep Sub-Micron FD-SOI MOSFETs

C. Baltaci1, Y. Leblebici1

1EPFL, Switzerland

Self-heating effects became more prominent with the introduction of the modern devices like FD-SOI and low thermal conductivity materials such as SiO2. Consequently, the temperature rise of a device due to its self-heating is pronounced more as the gate lengths shrink and the power density values increase. In analog design, one of the main drawbacks of elevated temperature is the deterioration of the thermal noise performance. For observing the thermal noise performance of FD-SOI MOSFETs, a thermal model for the device self-heating is used. The influence of self-heating on the thermal noise is examined by activating and inactivating the self-heating thermal model and comparing the results. It is shown that self-heating can deteriorate the thermal noise current (up to 18%) and input referred thermal noise voltage (up to 37%) significantly for short channel FD-SOI devices.


Influence of Layout and Technology Parameters on the Thermal Behavior of InGaP/GaAs HBTs

A. Catalano1, A. Magnani1, V. D'Alessandro1, L. Codecasa1, P. Zampardi2, B. Moser2, N. Rinaldi1

1University of Napoli "Federico II", Italy; 2Qorvo, Italy

This paper presents an extensive analysis aimed at quantifying the impact of all the key layout and technology parameters on the thermal behavior of InGaP/GaAs HBTs. The investigation is conducted by resorting to accurate 3-D numerical simulations performed in accordance to the Design Of Experiments technique.


Characterization of Electrical Crosstalk in 4T-APS Arrays using TCAD Simulations

J. Lopez-Martinez1, R. Carmona-Galan1, A. Rodriguez-Vazquez1

1Instituto de Microelectronica de Sevilla and University of Sevilla, Spain

TCAD simulations have been conducted on a CMOS image sensor in order to characterize the electrical component of the crosstalk between pixels through the study of the electric field distribution. The image sensor consists on a linear array of five pinned photodiodes (PPD) with their transmission gates, floating diffusion and reset transistors. The effect of the variations of the thickness of the epitaxial layer has been addressed as well. In fact, the depth of the boundary of the epitaxial layer affects quantum efficiency (QE) so a correlation with crosstalk has been identified.


Total Ionizing Dose Effects on CMOS Devices in a 110-nm Technology

E. Riceputi1, M. Manghisoni1, V. Re1, L. Gaioni1, R. Dinapoli2, A. Mozzanica2

1University of Bergamo, Italy; 2Paul Scherrer Institut, Switzerland

This paper presents a detailed characterization of CMOS devices belonging to a 110 nm CMOS technology process, in view of their application to the design of rad-hard front-end systems for the readout of pixel radiation detectors. The devices were evaluated before and after irradiation with a 10 keV X-ray beam, up to a Total Ionizing Dose of 5 Mrad. The results shown in this work are the first step of an activity aiming at studying the effects of ionizing radiation on the static and noise performance of the investigated technology.


15-MRad Radiation Dose Effect on GEMINI

L. Mangiagalli1, A. Pezzotta2, D. Tagnani3, G. Corradi3, F. Murtas3, G. Gorini1, A. Baschirotto1

1University of Milano Bicocca, Italy; 2EPFL, Switzerland; 3INFN Frascati, Italy

GEMINI front-end system is expected to be exposed to radiation for a Total Ionizing Dose (TID) up to 200krad during Triple-GEM detector usage. Analyzing effect of ionizing radiation on chip gives important information on chip robustness, critical for architecture validation. After irradiation for a total dose of 15 Mrad core elements of GEMINI channels still resulted to be functional. Test also highlighted critical points of the architecture that could be starting point to improve Triple-GEM front-end system radiation hardness.

15:00-16:20 Company Fair & SMACD Poster Session I
 Chair: Proff. G. Dundar, N. Horta, F. V. Fernandez

Low Power Comparator with Offset Cancellation Technique for Flash ADC

Mehdi Nasrollahpour, Rahul Sreekumar and Sotoudeh Hamedi-Hagh

San Jose State University, USA

The design and analysis of a low power comparator that features an offset cancellation technique has been carried out in this paper. The proposed low power circuit works in 1 GHz sampling frequency and developed in 65nm CMOS technology. An offset cancellation technique and a switch are added to the comparator to reduce the comparator offset and kickback noise. The comparator is implemented in a 5-bit Flash Analog to Digital converter (ADC) and the overall measured power consumption from 1 V power supply is 568 ?W. the proposed ADC can convert the analog input to digital output with 4.62 bits ENOB in Nyquist input frequency while the SNDR and SFDR are 29.6 dB and 42.4 dB, respectively.


Fast and Accurate Workload-Level Neural Network Based IC Energy Consumption Estimation

Nicoleta Cucu Laurenciu and Sorin Cotofana

Delft University of Technology, The Netherlands

A fast, yet accurate nanoscale IC energy estimation is a design-time desideratum for area-delay-power-reliability optimized circuits and architectures. This paper introduces an IC energy estimation approach, which instead of sequentially propagating workload vectors throughout the circuit, relies on an one time propagation of the workload statistics. To this end, the basic gates need be SPICE pre-characterized with respect to (w.r.t.) static and dynamic energy consumption per input transition type and Neural Network based gate models constructed and trained in order to estimate gate output statistics and consumed energy based on gate input statistics, i.e., the '0' -> '0', '0' -> '1', '1' -> '0', and '1' -> '1' transition probabilities. Both pre-characterization and training are done once per technology node and do not contribute to the actual evaluation time. In this way, regardless of n, the number of workload input vectors, by propagating signal statistics instead of logic values the overall circuit energy consumption is evaluated in one instead of n circuit traversals. Moreover, as opposed to the constant and equal gate delay assumption utilized in state of the art energy estimation methods, the proposed approach takes into account the real gate propagation delays, which yields estimates that are closer to the actual energy figures. We evaluated with the proposed method the static and dynamic energy consumption for a set of ISCAS'85 circuits and a 10,508-gate hashing circuit, using TSMC 40nm CMOS technology, and 50,000-vector workloads. The experiments indicate that our method provides an estimation error below 2.6% and 1.5% for dynamic and static energy, respectively, when compared to the accurate SPICE measurements, while providing an estimation speedup in the order of 50,000x.


Prediction of Chaotic Time-Series with Different MLE Values using FPGA-based ANNs

Ana Dalia Pano-Azucena1, Esteban Tlelo-Cuautle1,2, Luis Gerardo de La Fraga2, Carlos Sanchez-Lopez3, Jose De Jesus Rangel Magdaleno1 and Sheldon Tan4

1INAOE, Mexico; 2CINVESTAV, Mexico; 3Universidad Autonoma de Tlaxcala, Mexico; 4University of California at Riverside, USA

Chaotic time series can be generated from different kinds of chaotic oscillators in different dimensions and directions. However, their prediction becomes a challenge when they have different values of their maximum Lyapunov exponent (MLE), which is associated to the degree of unpredictability of a chaotic system. In this manner, we highlight how does an artificial neural network (ANN) can be used to predict chaotic time series with different MLE value. The cases of study are three chaotic time series with different MLE values, which are predicted by an ANN that is validated through measuring the mean square error (MSE) and root MSE (RMSE). We provide design and training details of a 5-layers ANN, and its implementation using field-programmable gate arrays. Finally, the ANN is validated with the prediction results that are compared to the original chaotic time series according to their MSE and RMSE.


Circuital Modelling for Electroporation

Stefania Romeo1 and Patrizia Lamberti2

1CNR, Institute for Electromagnetic Sensing of the Environment (IREA), Italy; 2DIEM, University of Salerno, Italy

The application of intense, short-duration pulsed electric fields to biological membranes induces an increase of their conductivity to external molecules, an effect termed electroporation (EP), which is currently exploited in several biomedical, industrial and environmental applications. The study of interaction mechanisms between pulsed electric fields and biological structures is addressed by experiments and modelling. In the latter case, analytical, circuital, numerical and molecular dynamics approaches have been proposed in the literature, providing complementary information on the EP phenomenon. In this paper, an overview on circuital modelling of EP is presented. In spite of the simplifications adopted from both a physical and electrical point of view, this approach is useful to perform rapid analysis on broad ranges of electrical parameters and provides aid to the optimization of the experimental design.


FEM-based numerical simulation supporting experimentally tested Electrochemotherapy protocols

Patrizia Lamberti1, Vincenzo Tucci1, Stefania Romeo2, Anna Sannino2, Olga Zeni2 and Maria Rosaria Scarfi2

1DIEM, University of Salerno, Italy; 2CNR, Institute for Electromagnetic Sensing of the Environment (IREA), Italy;

Electrochemotherapy (ECT) is a clinical procedure for the local treatment of solid tumors, which combines the application of pulsed electric fields (PEFs) and chemotherapeutic drugs, by exploiting the PEF-induced membrane permeabilization (electroporation, EP). The ESOPE pulsing protocol (8 pulses with 100 us duration and 1 kV/cm electric field strength, given at 1 Hz or 5 kHz as repetition rate) is the only protocol approved for application on human patients and is currently used in the clinical practice. Moving from an experimental study comparing the efficacy of ESOPE to that of modified PEF protocol with lower electric field intensity and higher pulse number, in this paper an electrophysiological model is used to provide theoretical support to the experimental results. The pore density and the transmembrane voltage time behavior at the upper pole of a single spherical cell are considered, in order to assess the EP effect of the applied pulse train, considered as boundary condition in the field based solution of the problem. The simulation results highlight that, 40 pulses 750 V/cm is a good candidate as ESOPE equivalent protocol.

16:40-18:00 Special Session on "Modeling diagnosis and control of PV systems"
Room #1 - VULCANO
 Chair: Prof. C. A. Ramos-Paja, Universidad Nacional de Colombia, Colombia

An improved method for quantifying degradation of photovoltaic modules

Antonino Laudani1, Gabriele-Maria Lozito1, Stefano Gaiotto1, Francesco Riganti-Fulginei1, Alessandro Salvini1, Ermanno Cardelli2, Antonio Faba2 and Simone Quondam2

1Roma Tre University, Italy; 2University of Perugia, Italy

In this paper an improvement of a two-indicators based method is presented for the quantification of photovoltaic (PV) modules degradation. These indicators are able to provide good estimation of the variations of series and shunt resistance of the one-diode model of the photovoltaic panels. This model is usually derived from the datasheet values of the PV panel. In this paper, a better performing procedure is proposed for the model identification. To provide accurate estimations it is expected to consider both module temperature and solar irradiance. For this reason, an effective procedure for sensing the actual solar irradiance is presented, allowing a completely on-line estimation of the module degradation that does not require any change in the module work point.


Energy Management System for an Isolated Microgrid with Photovoltaic Generation

Andres Camilo Henao-Munoz, Andres Julian Saavedra-Montes and Carlos Andres Ramos-Paja

Universidad Nacional de Colombia, Colombia

A comparison of two energy management systems for an isolated microgrid based on photovoltaic generation is presented in this paper. One energy management system is presented as an optimization problem solved by means of a mixed integer linear programming which aims to minimize the operating cost of the microgrid. The algorithm determines the optimal power dispatch of all distributed generation units using reduced linear models and operating constraints for each unit, together with a cost function, and historical information of meteorological and demand conditions. The simulation of the microgrid is carried out in Matlab. Results from the mixed integer linear programming are compared with results obtained from a proposed weighted algorithm, showing a reduction in the operating cost of the microgrid when the mixed integer linear programming algorithm is used; however, this algorithm spent more processing time than the weighted algorithm.


Modeling Cyber-Physical Systems for Automatic Verification

Youssef Driouich1, Mimmo Parente2 and Enrico Tronci3

1DIEM, University of Salerno, Italy; 2DISA-MIS, University of Salerno, Italy; 3Department of Computer Science, University of Rome "La Sapienza", Italy

In this paper we show how the open standard modeling language Modelica can be effectively used to support model-based design and verification of cyber-physical systems stemming from complex power electronics systems. To this end we present a Modelica model for a Distributed Maximum Power Point Tracking system along with model validation results.


Model of Series-Parallel Photovoltaic Arrays Designed for Parallel Computing

Juan David Bastidas-Rodriguez1, Daniel Gonzalez2 and Carlos Andres Ramos-Paja3

1Universidad Industrial de Santander, Colombia; 2Instituto Tecnologico Metropolitano, Colombia; 3Universidad Nacional de Colombia, Colombia

Photovoltaic (PV) arrays connected in Series-Parallel (SP) configuration are widely used in PV installations of different power levels. Accurate and low calculation time models of SP arrays are required for different applications; however, the models available in literature have a high computational burden due to the requirement of solving nested systems of nonlinear equations. This paper introduces a mathematical model for SP arrays designed for parallel computing to improve the calculation speed. For a given array voltage the current of each string is calculated by solving a nonlinear equation, which is independent from the other strings. Therefore, each nonlinear equation is solved in a different core and, finally, all the strings' currents are added to obtain the array current. Simulation results put into evidence the capacity of the proposed model to reproduce the characteristic curves of an SP array and the reduction in the calculation time with respect to an equivalent model available in literature.

16:40-18:00 Data Converters II
Room #2 - PANAREA
 Chair: Prof. F. Maloberti, University of Pavia, Italy

A Novel Architecture for a Capacitive-to-Digital Converter Using Time-Encoding and Noise Shaping

C. Rogi1, E. Prefasi2, R. Gaggl1

1Infineon Technologies, Austria; 2Universidad Carlos III de Madrid, Spain

This paper presents a Capacitive-to-Digital Converter (CDC) for MEMS sensors using a time-encoding approach. A common CDC needs an intermediate Capacitive-to-Voltage (C-V) stage to perform such a conversion. Instead, this architecture directly transforms the sensor capacitor quantity to a digital value. Additionally it is intended to give flexibility at reduced chip area. The proposed solution maps amplitude information into time domain using an integrating Dual-Slope (DS) converter. Furthermore, this CDC employs quantization error noise shaping to reduce measurement time. Both techniques, namely scaling of the CDC resolution and power consumption, will lead to an efficient implementation without extra cost in area. Auto-zeroing further suppresses the offset and low frequency noise of the amplifier. Simulation results show that a realization in digital CMOS technology will be a promising candidate for a scalable CDC for MEMS sensors.


A DAC-Assisted Speed Enhancement Technique for High Resolution SAR ADC

M. Kilic1, Y. Leblebici1

1EPFL, Switzerland

In this paper, a technique aiming at enhancing the conversion speed of asynchronous high resolution SAR ADCs is presented. In conventional SAR ADCs, the capacitive DAC size is growing exponentially with the converter resolution. The settling time of the MSB capacitors get thus longer, limiting the total conversion speed. This method proposes to operate a small and fast 3-bit ADC in parallel with the main one to determine rapidly the MSB values, while the capacitors of the main DAC have not settled yet. An error correction circuit detects and corrects automatically any decision error due to mismatch between the two DACs. A design example of a 10-bit ADC is implemented in 28nm FDSOI CMOS technology to illustrate this technique. A sampling rate of 800MS/s is achieved without any effort for reducing the capacitive DAC size.


Design of a Compact and Low-Power TDC for an Array of SiPM's in 110-nm CIS Technology

F. Bandi1, I. Vornicu1, R. Carmona-Galan1, A. Rodriguez-Vazquez1

1Instituto de Microelectronica de Sevilla and University of Sevilla, Spain

Silicon photomultipliers (SiPM's) are meant to sub- stitute photomultiplier tubes in high-energy physics detectors and nuclear medicine. This is because of their - to name a few inter - esting properties - compactness, lower bias voltage, tolerance to magnetic fields and finer spatial resolution. SiPM's can also be built in CMOS technology. This allows the incorporation of active quenching and recharge schemes at cell level and processing circuitry at pixel level. One of the elements that can lead to finer temporal resolutions is the time-to-digital converter (TDC). In this paper we describe the architecture of a compact TDC to be included at each pixel of an array of SiPM's. It is compact and consumes low power. It is based on a voltage controlled oscillator that generates multiple internal phases that are interpolated to provide time resolution below the time delay of a single gate. Simulation results of a 11b TDC based on a 4-stage VCRO in 110nm CIS technology yield a time resolution of 75ps, a DNL of +/-0.36 LSB, a INL +/-0.69 LSB, and a power consumption of 880μW.


A General Formula for Impulse-Invariant Transformation for Continuous-Time Delta-Sigma Modulators

J. Talebzadeh1, I. Kale1

1University of Westminster, United Kingdom

This paper presents a generalised new formula for impulse-invariant transformation which can be used to convert an nth-order Discrete-Time (DT) ΔΣ modulator to an nth-order equivalent Continuous-Time (CT) ΔΣ modulator. Impulse-invariant transformation formulas have been published in many open literature articles for s-domain to z-domain conversion and vice-versa. However, some of the published works contain omissions and oversights. To verify the newly derived formulas, very many designs of varying orders have been tested and a representative 4th-order single-loop DT ΔΣ modulator converted to an equivalent CT ΔΣ modulator through the new formulas are presented in this paper. The simulation results confirm that the CT ΔΣ modulator which has been derived by these formulas works in accordance with the initial DT specifications without any noticeable degradation in performance in comparison to its original DT ΔΣ modulator prototype.

16:40-18:20 Analog Circuits II
Room #3 - LIPARI
 Chair: Prof. G. Palmisano, University of Catania, Italy

A 0.9-V 600-MHz 4th-Order Analog Filter with Feed-Forward Compensated OPAMP in CMOS 28 nm

F. Ciciotti1, M. De Matteis1, A. Baschirotto1

1University of Milano Bicocca and INFN Milano Bicocca, Italy

In this paper a 600MHz 4th order low-pass analog filter in CMOS-28nm is presented. The transfer function is obtained with the cascade of two Active-RC Rauch biquadratic cells. Each cell is based on a novel OPAMP optimized for very high frequency operation achieving an Unity Gain Band Width (UGBW) > 7GHz. The developed three stage folded OPAMP exploits a feed-forward compensation technique to maximize bandwidth and an improved Common Mode Feedback Circuit (CMFB) necessary to reduce parasitic poles and to guarantee acceptable CMFB phase margin. The OPAMP is able to manage the very low VDD/VTH ratio of the 28nm process lowering its input common mode voltage in respect with input and output common mode voltage of the whole filter. The prototype consumes 11.4mW from a single 0.9V supply voltage, achieving 600MHz of bandwidth with an in-band integrated noise of 750uVRMS. The IIP3 calculated at 300&350MHz is 12.5dBm


A 1.2-V Bandgap Reference with an Additional 29.6-ppm/°C Temperature Stable Output Current

M. Hanhart1, R. Wunderlich1, S. Heinen1

1RWTH Aachen University, Germany

This paper presents a precise 1.175 V voltage reference bandgap circuit with an additional temperature compensated current output for DC-DC switch mode converters. The nominal temperature coefficient (TC) of the bandgap voltage is 13 ppm/°C from −40°C to 140°C. With the proposed circuit architecture output voltage deviations as low as +/-18 mV (+/-3 σ) from the nominal bandgap voltage are achieved. The reference output current measures 1 μA with a temperature stability of 29.6 ppm/°C. The circuit is designed in a 0.18 μm HV-CMOS process to operate from a 1.8 V supply voltage with a simulated overall current consumption of approximately 50 μA. The pro- posed bandgap reference circuit occupies a silicon die area of 0.05 mm^2 .


A Stable CMOS Current Reference Based on the ZTC Operating Point

Y. Wenger1, B. Meinerzhagen1

1TU Braunschweig, Germany

This paper presents the design of a temperature stable, supply independent current reference in a 0.25μm CMOS technology. A current with small temperature coefficient is derived by exploiting the zero temperature coefficient (ZTC) operating point of a MOS transistor. The transistor is used in a feedback loop to cancel the temperature dependence of a polysilicon resistor. It is shown that simple equations together with fast simulations of the ZTC point and a special temperature coefficient can quickly yield an accurate design. Measurements from 10 samples show an average current of 6μA with a standard deviation of 2.3%, a voltage dependence of 0.3%/V whereas the temperature coefficient is approximately 130ppm/°C measured over a temperature range from -40°C to 125°C. The circuit compares favorably with other published untrimmed current references.


Improved Common-Mode Feedback Based on LCMFB Techniques

M. Garde1, A. Lopez-Martin1, J. Ramirez-Angulo2

1Public University of Navarra, Spain; 2New Mexico State University, United States

A class AB Differential Difference Amplifier (DDA) for continuous-time common-mode feedback is presented. It employs Local Common-Mode Feedback (LCMFB) to improve GBW and dynamic performance of the common-mode feedback loop, without increasing static power consumption or supply voltage requirements. Simulation results in a 0.5 μm CMOS process show an increase in open loop DC gain (ADC) of 15.3 dB and also in gain- bandwidth product (GBW) by a factor of 5.5, respectively. Additionally, measurement results for a 0.5 μm CMOS test chip prototype validate the proposal.


A Standard CMOS Bridge-Based Analog Interface for Differential Capacitive Sensors

G. Barile1, G. Ferri1, F. Parente1, V. Stornelli1, A. Depari2, A. Flammini2, E. Sisinni2

1University of L'Aquila, Italy; 2University of Brescia, Italy

This work describes an analog electronic interface, based on a modified De Sauty AC bridge, performing a differential capacitive sensor estimation. A suitable feedback loop tunes a Voltage Controlled Resistor so to balance the bridge. The electronic circuit has been designed in a standard integrated CMOS technology (AMS 0.35μm) with a low supply voltage (+/-1.5 V) and a reduced power consumption (lower than 4mW). PSpice simulation results show a very good agreement with theoretical expectations. The output voltage accuracy shows a 30 mV maximum absolute error for a range of +/-50% of sensor variations from its baseline value. Since very small baseline values are allowed (lower than tens of μF), the interface is suitable for hosting MEMS devices.

16:40-18:10 COMPETITION Session II
Room #4 - Plenary room
 Chair: Prof. R. Sommer, Technical University Ilmenau, Germany

A Cryogenic Modeling Methodology of MOSFET I-V Characteristics in BSIM3

Aykut Kabaoglu and Mustafa Berke Yelten

Istanbul Technical University, Turkey

Transistor models for circuit analysis have temperature dependent parameters which are only valid in standard temperature range of 55C to 125C in general. Circuits designed for low temperature military and space applications should work in cryogenic conditions properly. Thus, transistor models must be modified. In this paper, a methodology has been developed to optimize these parameters for MOSFET devices at low temperatures. The methodology updates all parameters regulating the temperature dependency of the drain current, threshold voltage and saturation velocity based on the chosen target data set taken at low temperature. An automated system involving a circuit simulator and mathematical programming tool has been established that can analytically compute revised model parameters independent of the transistor process. Using this methodology, average errors in I-V curves of various sizes NMOS and PMOS transistors for 0.18um technology has been reduced below 2.5% and 3.5%, respectively.


TARS: A Toolbox for Statistical Reliability Modeling of CMOS Devices

Javier Diaz-Fortuny1, Javier Martin-Martinez1, Rosana Rodriguez-Martinez1, Montse Nafria-Maqueda1, Rafael Castro-Lopez2, Elisenda Roca-Moreno2 and Francisco V. Fernandez-Fernandez2

1Universitat Autonoma de Barcelona (UAB), Spain; 2Instituto de Microelectronica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Spain

This paper presents a toolbox for the automation of the electrical characterization of CMOS transistors. The developed software provides a user-friendly interface to carry out different tests to evaluate time-zero (i.e., process) and time-dependent variability in CMOS devices. Also, the software incorporates a post-processing capability that allows users to visualize the data. Moreover, without loss of generality, the toolbox allows the user, from the measured data, to feed a particular physics-based model that accounts for various aging phenomena.


CASE: A Reliability Simulation Tool for Analog ICs

Pablo Martin-Lloret1, Antonio Toro-Frias1, Rafael Castro-Lopez1, Elisenda Roca Moreno1, Francisco V Fernandez1, Javier Martin-Martinez2, Rosana Rodriguez Martinez2 and Montserrat Nafria Maqueda2

1Instituto de Microelectronica de Sevilla, Spain; 2Universitat Autonoma de Barcelona, Spain

With the evolution in the scale of integration in ICs, aging-related problems are becoming more important and, nowadays, solutions to cope with these issues are not yet mature enough, especially in the field of analog circuit simulation. CASE, the novel simulator presented in this paper, can evaluate the impact of reliability effects in analog circuits through a stochastic physic-based model. The implemented simulation flow is accurate and efficient in terms of CPU. The two main improvements over currently reported and commercial tools, is that the simulator can simultaneously take into account both time-zero and timedependent variability, and that an adaptive method, to account for the strong link between biasing and stress, can improve the accuracy while keeping acceptable CPU times.

Thursday, June 15th
10:20-12:00 High-Speed Circuits and Systems
Room #1 - VULCANO
 Chair: Prof. P. Palestri, University of Udine, Italy

A Low Noise Front-End Trans-Impedance Amplifier Channel for a Pulsed Time-Of-Flight Laser Radar

A. Baharmast1, J. Kostamovaara1

1University of Oulu, Finland

A low noise front end trans-impedance amplifier for a pulsed time-of-flight laser range finder receiver is presented. The architecture is based on unipolar-to-bipolar pulse shaping immediately at the input of the receiver channel, where the received unipolar current pulse is converted to a bipolar current to be fed to the trans-impedance amplifier (TIA). An extensively wide dynamic range is achieved using the proposed pulse shaping scheme and TIA realization. As the timing point is located at the first zero crossing point of the bipolar signal, the non-idealities of the TIA have little effect on it. Simulations show the walk error of the TIA channel to be less than +/-40ps in the dynamic range 1:100000. The input-referred noise current and bandwidth are 72nA and 415MHz, respectively.


A FPGA Correlation Receiver for CDMA Encoded LiDAR Signals

T. Fersch1, M. Alam1, R. Weigel2, A. Koelpin2

1Robert Bosch, Germany; 2University of Erlangen-Nuremberg, Germany

We present a digital implementation of a correlation receiver for pulsed CDMA lidar signals in direct-time-of-flight systems. A coded time-of-flight lidar is capable to identify its own signals and to reject state-of-the-art uncoded or differently coded pulses. The required sampling rate of the system ADC is determined. For processing the digitized receive signal a correlation filter realized in FPGA hardware is presented. A single filter running at the maximum viable FPGA clock rate of 200 MHz does not ensure reliable signal detection. The filter was parallelized five times to allow processing of 1000 MSa/s signals. Simulations with experimental coded lidar data prove the system's code separation properties.


Compact Dual-Wavelength System for Time-Resolved Diffuse Optical Spectroscopy

M. Renna1, M. Buttafava1, E. Martinenghi1, M. Zanoletti1, A. Dalla Mora1, A. Pifferi1, A. Torricelli1, D. Contini1, F. Zappa1, A. Tosi1

1Politecnico di Milano, Italy

We present a compact instrument for time-resolved diffuse optical spectroscopy based on two pulsed diode lasers, a Silicon PhotoMultiplier working in single-photon regime and a custom-made Time-to-Digital Converter. The temporal width of the Instrument Response Function is narrower than 300 ps (Full-Width at Half Maximum) and the time measurement unit exhibits 10 ps temporal resolution with a Full Scale Range of 80 ns. The laser pulses are injected into the sample through two 400 μm core optical fibers and re-emitted light is collected by 1 mm core plastic optical fiber aligned with detector active area. The instrument is housed in a compact 200 x 160 x 50 mm3 metal case, weighs less than 2 kg and requires a single 15 V DC voltage power supply, with a power consumption lower than 10 W, thus being suitable for battery operation. The long-time measurement stability makes the system ideal for monitoring applications on the field, where state-of-the-art bulky time-resolved systems cannot be exploited.


System and Transistor-Level Analysis of a 8-Tap FFE 10-GB/s Serial Link Transmitter with Realistic Channels and Supply Parasitics

A. Bandiziol1, W. Grollitsch2, F. Brandonisio2, R. Nonis2, P. Palestri1

1University of Udine, Italy; 2Infineon Technologies, Austria

Circuit/system level simulations are employed to assess the performance of a 10 Gbps transmitter for a high speed serial interface to be used in automotive Electronic Control Units. The transmitter has been designed in a standard 28 nm technology and features feed-forward equalization (FFE) with 8 taps (1 pre- and 6 post-cursors), whose strength is programmable with 16 discretization steps. It is shown that the parasitic inductance on the supply terminals degrades the performance in terms of jitter and SNR and tends to hamper the benefits of FFE. When the value of these inductances is minimized, system-level models of the transmitter reproduce quite well time-consuming transistor-level simulations.


Analysis, Optimization, and Modeling of Analog Multi-Tone Serial Data Transceivers

G. Kim1, K. Gharibdoust2, Y. Leblebici1

1EPFL, Switzerland; 2Kandou Bus, Switzerland

This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, which is not straightforward to model and hard to optimize with conventional serial link modeling tools. A method to limit the computing system's memory usage when simulating a data transmission of a long bit-stream, e.g., >10Mbits, is also described. The reliability of the modeling framework is proven by some comparisons with a highly-trusted commercial tool for a conventional TRX architecture.

10:20-12:00 Biomedical Circuits and Applications
Room #2 - PANAREA
 Chair: Prof. P. Malcovati, University of Pavia, Italy

Tapering of Nanoelectrodes for an Intracellular Contact via a Double Hard Mask Technique

S. Allani1, A. Jupe1, M. Figge1, A. Goehlich1, H. Vogt1

1Fraunhofer IMS, Germany

To realize an intracellular contact between nanoelectrodes and cells, a sufficient small electrode diameter is needed [1]. A sacrificial layer process developed by the Fraunhofer IMS using deep reactive ion etching and atomic layer deposition [2] is varied using a double hard mask technique to taper structures in a sacrificial layer and thereby the nanoelectrodes' diameter. The principles and evaluation of the spacing technique are presented here. [1] O. Staufer et al., "Functional fusion of living systems with sythetic electrode interfaces", Beilstein J. Nanotechnol., vol. 7, pp. 296-301, 2016 [2] A. Jupe, M. Figge, A. Goehlich and H. Vogt, "Post-CMOS integrated ALD 3D micro- and nanostructures and application for multi-electrode arrays," GMM-Fachbericht 86: Mikro-Nano-Integration, pp. 115-118, 2016


Design of a CMOS Image Sensor and Stimulation IC for a Wide-Angle Retina Implant

P. Raffelberg1, F. Waschkowski2, R. Viga1, W. Mokwa2, P. Walter2, R. Kokozinski3

1University of Duisburg-Essen, Germany; 2RWTH Aachen University, Germany; 3Fraunhofer IMS, Germany

In this work the design of a new epiretinal stimulator approach with integrated bendable imaging sensor is presented. First, the fundamental differences to the existing retinal stimulation implants is described. In the second part, a brief description of the novel designed implant is given, where several integrated circuits are placed on a single polyimide foil to create the mechanically flexible implant. Then the design of the developed dies is presented, containing the image sensor with a signal processing unit, a configurable waveform generator and a current controlled stimulation unit.


Compact Pixel Architecture for CMOS Lateral Flow Immunoassay Readout Systems

E. Pilavaki1, W. Serdijn2, A. Demosthenous1, V. Valente1

1University College London, United Kingdom; 2TU Delft, Netherlands

A novel pixel architecture for CMOS image sensors is presented. It uses only one amplifier for both integration of the photocurrent and in-pixel noise cancelation, thus minimizing power consumption. The circuit is specifically designed to be used in readout systems for lateral flow immunoassays. In addition a switching technique is introduced enabling the use of column correlated double sampling technique in capacitive transimpedance amplifier pixel architectures without the use of any memory cells. As a result the reset noise which is crucial in these architectures can be suppressed. The circuit has been designed in a 0.35-μm CMOS technology and simulations are presented to show its performance.


Capacitance Measurement Applied to the Medical Injection Pen

S. Joly1, A. Wienhues1, C. Dehollain2

1Valtronic Technologies, Switzerland; 2EPFL, Switzerland

Many drugs need to be injected frequently by the patient himself, e.g. insulin for diabetes treatment. Disposable injection pens comprise the most popular delivery devices for ease of use and discretion. However, these devices do not provide any tracking capability. In this paper we present a method to measure automatically the injected dose based on a capacitive measurement. A typical dose of e.g. 2 IU insulin (volume of 20.8μl) can be accurately detected corresponding to a capacitance change of 11.82fF at a standard deviation of 4.89 fF for 5 consecutive injections. This paper will focus on the design of the electrodes and the feasibility of the capacitive tracking method.


A Closed-Loop System for Neural Networks Analysis through High Density MEAs

G. Seu1, G. Angotzi2, G. Tuveri1, L. Raffo1, L. Berdondini2, A. Maccione2, P. Meloni1

1University of Cagliari, Italy; 2Istituto Italiano di Tecnologia, Italy

In this work we present a FPGA-based system for real-time processing of neural signals acquired by commercial high-density microelectrode array (HDMEA). The considered MEA features 4096 electrodes with 18kHz sampling frequency and 12-bit resolution, thus produces nearly 1 Gbps of data. Within the implementation, we considered low-latency as a main objective, to allow for closed-loop acquisition-stimulation experiments, that represent a novel promising frontier in neurophysiology and in the development of brain-machine interfaces. The developed platform is implemented on a low-to-mid Zynq all-programmable SoC, and is able to perform all the required computation (from signal acquisition to response generation) with less than 2ms latency, enabling closed-loop applications in a wide range of experiments.

10:20-12:00 Power Circuits and Harvesting
Room #3 - LIPARI
 Chair: Dr. E. Ragonese, STMicroelectronics, Italy

Integrated Transformer Modelling for Galvanically Isolated Power Transfer Systems

N. Greco1, A. Parisi1, N. Spina2, E. Ragonese2, G. Palmisano1

1University of Catania, Italy; 2STMicroelectronics, Italy

This work presents a review of integrated transformers for galvanic isolation with particular focus on their modelling in power transfer systems. A comparison between transformer-coupled oscillator topologies is carried out, highlighting the main differences in the realization of the isolation transformers. A novel lumped geometrically scalable model of three-windings transformer for current-reuse hybrid-coupled oscillators has been developed and compared with previously reported models. This transformer has been validated by means of electromagnetic simulations in a wide range of geometrical parameters, achieving an absolute error lower than 8% for inductance, Q-factor peak, self-resonance frequency, and magnetic coupling factor.


A Reduced Output Ripple Step-Up DC-DC Converter for Automotive LED Lighting

P. Giannelli1, L. Capineri1, G. Calabrese2, G. Frattini2, M. Granato2

1University of Firenze, Italy; 2Texas Instruments, Italy

This works presents the design and test of a switching power supply intended for supplying LED tail lights in automotive applications. The design is proposed as an alternative to an existing Boost reference design, and is based on a different step-up topology, the ZetaBoost, with the objective of reducing the output ripple, and therefore ease the compliance with automotive regulations.


Adaptive Current Source Driver for High-Frequency Boost Converter to Reduce EMI Generation

V. Subotskaya1, B. Deutschmann2

1Infineon Technologies, Austria; 2TU Graz, Austria

The reduction of electromagnetic emissions (EME) in switch mode power supplies (SMPS) has high importance especially in automotive applications. The main methods to influence the switching behaviour of SMPS are external filters, spread spectrum techniques and the output driver circuits. This paper presents the concept and it's implementation of an output driver with adaptive current source control for high frequency boost converter. The advantage of proposed circuit in comparison to the previous solutions is adjusted driver gate current based on the information of the gate voltage slope without involving the complex digital control scheme which requires to sense and to digitize the information of the switching current, switching node voltage and gate voltage. Into addition, the concept allows to control the driver switching time independently from external parameters (temperature, input voltage, load current). The proposed concept implementation is for 8V output voltage, 500kHz switching frequency boost converter.


An All-MOS Low-Power Fast-Transient 1.2-V LDO Regulator

J. Perez-Bailon1, A. Marquez1, B. Calvo1, N. Medrano1

1University of Zaragoza, Spain

This paper presents a fully integrated low-power 0.18 um CMOS Low-Dropout (LDO) voltage regulator for battery-operated portable devices. A single stage high-gain folded cascode-compensated amplifier is used to attain good static performances, while thanks to a very simple dynamic bias circuit, transient performances are significantly enhanced. Results validate a 1.2 V output voltage from a 3.3 V to 1.3 V battery input voltage, delivering a load current of 50 mA over a 50 pF load. The quiescent current is only 5.9 uA, including an all-MOS 0.4 V reference voltage. Settling times are lower than 5.4 us at full load transient.


5-Level E-Type Back to Back Power Converetrs - A New Solution for Extreme Efficiency and Power Density

M. Di Benedetto1, P. Grbovic2, L. Solero1, A. Lidozzi1, F. Crescimbini1

1University of Roma Tre, Italy; 2Huawey, Germany

A novel solution to high efficiency and high specific power three-phase Back to Back Power Converters has been proposed and theoretically investigated in this paper. Target applications are variable speed gen-sets, electric drives and independent power supplies. The solution proposed is based on a novel 5-Level E-Type topology. Advantages of the new solution, such as significant reduction of the input/output filter size/weight and switching losses have been theoretically investigated. A typical 20kVA independent gen-set power supply application has been analyzed as a case study. An extraordinary double conversion efficiency of 98.6% and specific power of 5kVA/kg have been achieved. The design results has been confirmed by set of Plexim/PLECS simulations. Experimental results will be presented in the final paper.

10:20-12:00 Modeling
Room #4 - Plenary room
 Chair: Prof. L. Hedrich, Goethe-University of Frankfurt/M., Germany

Comparing Apples and Oranges: Evaluating Model-Coverage using Acceptance Regions

Martin Grabmann and Georg Glaser

Insitut fur Mikroelektronik und Mechatronik Systeme gemeinnutzige GmbH, Germany

Analog/Mixed-Signal (AMS) design and verification is dominated by modelling tasks. Model validity is crucial for the design's correctness but lacks a more formal criterion. We propose a novel model verification strategy to evaluate the coverage with respect to a given circuit. We define model-coverage based on the individual acceptance regions in parameter space. This imposes a measure that can be formally described and efficiently approximated by an industrial simulation environment. We prove the ability of our approach in a case study: A model of a clock-recovery component used in RFID tags is compared to the realized circuit and layout. Using the novel coverage measure, we match the model to the circuit: By systematically adding new constraints to the model code, the coverage is increased to 99% ensuring the correctness of the overall system verification.


Comparing Code Coverage Metrics for Analog Behavioral Models

Andreas Furtig, Moritz Paschke and Lars Hedrich

University of Frankfurt, Germany

In current applications Analog/Mixed-Signal (AMS) circuits gets increasingly demanding. To speed up the design process parts of the design were implemented in hardware description languages. Besides positive aspects like simulation processing times these models need to be checked in terms of verification run set completeness, i.e. input stimuli, parameter setting, and testbench circuitry. For this purposes we present a methodology to adopt code coverage metrics on Verilog-A models. A public domain analog circuit simulator automatically instruments and executes the behavioral description. The coverage results are automatically annotated and compared to a coverage metric based on the reachable analog state-space of the circuit. We discuss the methodology on several examples and sketch a path to improve the completeness of a verification run set.


Realistic Worst-Case Parameter Sets for MEMS Technologies

Andreas Herrmann1, Christof Hielscher2, Alexander Mueller2, Gisbert Hoelzer2 and Helmut Graeb1

1Technical University of Munich, Germany; 2X-FAB Semiconductors Foundries AG, Germany

Since MEMS systems get more and more complex their design needs accurate consideration of the worst-case conditions. This paper introduces a realistic worst-case characterization from IC design to the MEMS manufacturing process. It is based on the joint distribution of process parameters and on the sensitivity analysis of circuit performance and provides an improved worst-case characterization to classical corner cases. It is illustrated with an industrial MEMS technology and an acceleration sensor.


Importance of IR Drops on the Modeling of Laser-Induced Transient Faults

Raphael Viera1,2,3, Philippe Maurine1, Jean-Max Dutertre2 and Rodrigo Possamai Bastos3

1LIRMM, CNRS, UMR N5506, France; 2Ecole Nat. Sup. des Mines de St-Etienne, France; 3Univ. Grenoble Alpes, CNRS, TIMA, Grenoble, France

Laser fault injection attacks induce transient faults by locally generating transient currents capable to temporarily flip the outputs of several gates. Many models used to simulate transient faults induced by laser consider several elements to better represent the effects of the laser on ICs. However, a laser-induced current between VDD and GND, which provokes significant IR-drops, has been neglected. This paper highlights the importance of the induced IR-drops on the modeling of laser-induced transient faults by using IR drop CAD tools. It also shows that laser-induced IR drops can be sufficiently strong to produce alone transient faults. As a result, the number of faults on a case-study circuit is accentuated whether IR drop effects are taken into account.


On the Accurate Modeling of Analog Circuits via the Kriging Metamodeling Technique

Amel Garbaya1, Mouna Kotti2, Mourad Fakhfakh1 and Esteban Tlelo-Cuautle3

1University of Sfax, Tunisia; 2University of Sousse, Tunisia; 3INAOE, and CINVESTAV, Mexico

This work deals with the application of the Kriging technique for the accurate modeling of analog circuits, namely, a CMOS second generation current conveyor, and a CMOS voltage follower. Three types of correlation functions are used for this purpose: the Spline, the Gaussian and the Exponential Correlation functions. A comparative study is given. Two metrics are used; Root Mean Square Error and the Maximum Absolute Error. Obtained results show that the Gaussian correlation function provides better results regarding the accuracy of the constructed models, when compared to the other functions.

13:20-15:00 Circuits for Memories and Security
Room #1 - VULCANO
 Chair: Prof. G. Palumbo, University of Catania, Italy

Reconfigurable Array-Based Design for Flexible Cryptography Chip Architecture

J. Jeong1, J. Kim1, T. Kim1, J. Choi1

1Kyungpook National University, South Korea

In this paper, we present an area efficient crypto chip for sharing and selecting the hardware operation of the block cipher (ECC, AES, ARIA, and HIGHT) and reconfigurable crypto chip of an array-processor-based cryptography algorithm. Based on the proposed processor, we designed an encryption chip that reduced the total area of ECC, AES, ARIA and HIGHT by 21% using 0.18um CMOS technology. Also, Cryptography Array Processor (CAP) of ECC, AES, ARIA, and HIGHT indicates high performance at 40Kbps, 1,085 Mbps, 746 Mbps and 178 Mbps respectively. The proposed design of crypto chip shows the flexibility of the encryption algorithm and high hardware performance.


Fully Integrable Current-Mode Feedback Suppressor as an Analog Countermeasure against CPA Attacks in 40-nm CMOS Technology

D. Bellizia1, G. Scotti1, A. Trifiletti1

1University of Roma "La Sapienza", Italy

Security of sensible data for ultraconstrained IoT smart devices is one of the most challenging task in modern design. The needs of CPA-resistant cryptographic devices has to deal with the demanding requirements of small area and small impact on the overall power consumption. In this work, a novel current-mode feedback suppressor as on-chip analog-level CPA countermeasure is proposed. It aims to suppress differences in power consumption due to data-dependency of CMOS cryptographic devices, in order to counteract CPA attacks. The novel countermeasure is able to improve MTD of unprotected CMOS implementation of at least three orders of magnitude, providing a x1.1 area and x1.7 power overhead.


A 200-MHz, 0.65-fJ/(Bit Search), 1.152-kBit Pipeline Content Addressable Memory in 28-nm CMOS

F. Fary1, L. Mangiagalli1, A. Pipino1, F. Resta1, M. De Matteis1, A. Baschirotto1

1University of Milano Bicocca, Italy

In this paper a complete design of a Content Addressable Memory (CAM) in bulk-CMOS 28nm technology is presented. The CAM has 64x18 bit resolution, operates at 200MHz and exploits the low power pipeline searching algorithm. Dedicated circuital solutions have been adopted to mitigate the well-known issues in CMOS 28nm-bulk technology (like higher sensitivity to Process-Voltage-Temperature variations, increased gate serie resistance, very low supply voltage vs. threshold voltage, etc ). This allows to take advantage of the larger transition frequency available in nm-range technologies and the lower parasitic capacitances. Simulation results (based on post-layout extracted schematic) have been carried out, validating this way the hereby proposed CAM design. Overall average power consumption is 153uW, corresponding to 0.65fJ/(BitּSearch), one of the higher Figure-of-Merit comparing with similar CAM architectures available in literature. Total area occupancy for 1.152kb resolution is 0.015mm2.


Impact of the Erase Algorithms on Flash Memory Lifetime

G. Alieri1, G. Giaconia1, L. Mistretta1, F. La Rosa2, A. Cimino2

1University of Palermo, Italy; 2STMicroelectronics, Italy

This paper presents a comparative study on the impact of the erase algorithm on flash memory lifetime, to demonstrate how the reduction of overall stress, suffered by memories, will increase their lifetime, thanks to a smart management of erase operations. To this purpose a fixed erase voltage, equal to the maximum value and the maximum time-window, was taken as the reference test; while an algorithm with adaptive voltage levels and the same overall time-window was designed and implemented in order to compare their experimental results. This study was carried out by using an innovative Automated Test Equipment, named Portable-ATE, tailored for Memory Test Chip and designed for performance evaluation at research and development (R&D) level, where testing adaptability, configurability together with capability to get immediate results are the most significant [1-3]. The results show how the adoption of the smart adaptive algorithm allowed to increase the attainable erasing cycles from 750 thousands to a total number well beyond 1 million cycles.


A Low-Complexity Programmable Current Mode Circuit to Design the Sawtooth Chaotic Map

T. Addabbo1, A. Fort1, M. Mugnaini1, S. Rocchi1, H. Takaloo1, V. Vignoli1, N. Petra2

1University of Siena, Italy; 2University of Napoli "Federico II", Italy

We propose a programmable low-complexity current mode circuit to implement a controllable chaotic Sawtooth map, to take into account and correct the effects of the fabrication process variability, mismatches and temperature variations. The proposed solution, simulated using Cadence Virtuoso and a 0.35μm mixed-signal CMOS technology provided by AMS, is presented and discussed with theoretical arguments.

13:20-15:00 Energy management
Room #2 - PANAREA
 Chair: Prof. F. Baronti, University of Pisa, Italy

Tuning of Moving Window Least Squares-based Algorithm for Online Battery Parameter Estimation

Rocco Morello, Roberto Di Rienzo, Roberto Roncella, Roberto Saletti and Federico Baronti

University of Pisa, Italy

Online battery parameter identification algorithms, such as the Moving Window Least Squares, allow model-based state estimators with low computational intensity to be very accurate. This paper presents a procedure for tuning the algorithm’s parameters by using application-specific current profiles. A gardening application is taken as a case study. The results prove the validity of the proposed procedure and allow us to assess the identification algorithm performance.


Impact of Receiver Conversion Configuration on the Efficiency of Wireless Power Transfer Systems

Nicola Femia and Giulia Di Capua

DIEM, University of Salerno, Italy

This paper investigates the impact of the receiver conversion configuration on the efficiency of Wireless Power Transfer Systems (WPTSs). Post-Regulated Synchronous Rectifier (PRSR) and Controlled Synchronous Rectifier (CSR) configurations are analyzed and compared with reference to a battery charger application. A WPTS model including conduction and switching losses is adopted to analyze the operation range and the efficiency of the two configurations. A 2W@6.78MHz battery charger is adopted as WPTS test bench, with coils coupling coefficient ranging from 0.03 to 0.09. The results of simulations show that the PRSR and the CSR have dual performances in terms of efficiency and operability with respect to the coupling coefficient and the load current level.


Simulation Platform for Analyzing Battery Parallelization

Roberto Di Rienzo, Federico Baronti, Roberto Roncella, Rocco Morello and Roberto Saletti

University of Pisa, Italy

This paper discusses a simulation platform for predicting the behavior of a battery system comprising two batteries, which can be parallelized in a controllable way. The model of the battery, the load and the parallelization algorithm is developed and simulated in MATLAB Simulink environment. The simulation platform and the proposed parallelization algorithm are validated in a real gardening application. The simulation results prove to be useful for further investigation into the benefits of battery parallelization in terms of reduced battery aging and improved energy efficiency.


ECP Technique Based Capacitor-Less LDO with High PSRR at Low Frequencies, -89dB PSRR at 1MHz and Enhanced Transient Response

Mehdi Nasrollahpour1, Sotoudeh Hamedi-Hagh1, Yasin Bastan2 and Parviz Amiri2

1San Jose State University, USA; 2SRTTU, Iran

An external capacitor-less low dropout (LDO) voltage regulator with high PSRR and enhanced transient response is presented. The novel idea is applying a replica circuit which can pull excessive current. Excessive Current Pulling (ECP) technique decreases the equivalent output impedance to enhance transient response. The proposed LDO has been simulated in 0.18 ?m CMOS Technology. Its regulated output voltage is 1.6 V with the power supply of 1.8 V. The proposed technique has the advantages of simulated PSRR of -88.7 dB at 1 MHz and –67 dB at 100 KHz. Overshoots and undershoots are less than 45.2 mV and 30 mV under the load varies from 50 mA to 0 mA with rise/fall time of 100ns, respectively. Simulation results show that the achieved line regulation is 28.3 mV/V and the load regulation is 0.33 %/mA.


Harmonic Analysis of Diode-Bridge Rectifiers in Wireless Power Transfer System

Nicola Femia, Giulia Di Capua and Ricieri A. Pessinatti Ohashi

DIEM, University of Salerno, Italy

This paper discusses a model for the harmonic analysis of full bridge diode rectifiers in Wireless Power Transfer Systems (WPTSs). The proposed model is based on an iterative algorithm which identifies the zero crossing of diodes currents, including the threshold voltage, the state-dependant differential resistance and the parasitic capacitance of diodes. The algorithm has been solved in MATLAB and the results of the analysis of a 2W@6.78MHz WPTS in different load conditions are compared with PSIM simulations and experimental results.

13:20-15:00 Variability and reliability
Room #3 - LIPARI
 Chair: Dr. R. Martins, University of Lisbon, Portugal

Improving ICs reliability with high speed thermal mapping

Saverio Panarello1, Claudia Triolo1, Francesca Garesci1, Salvatore Patane1, Giuseppina Bille2, Davide Patti2, Lukas Burian2, Daniela Gazzo2, Sandor Petenyi2 and Calogero Ribellino2

1University of Messina, Italy; 2STMicroelectronics, Italy

The power elements are the weak parts of integrated circuits (ICs), in fact, through these elements the power is usually dissipated as heat. This provides two effects: non-uniform generation of the heat across the die and temperature gradients. Understanding this phenomena is very important for choosing the right location of sensitive components, like thermal sensors, in order to improve reliability. Furthermore, an accurate thermal modeling for reliability evaluations can be obtained and validated if the temperature distribution on the chip is experimentally measured, reconstructing the thermal maps. Here, we propose a suitable instrument to perform a direct measure of thermal distributions. The instrument has to be able to recognize small partitions of the chip and to store fast thermal events in the range below us. With its application, a great improvement can be obtained for ICs reliability.


Including a Stochastic Model of Aging in a Reliability Simulation Flow

Antonio Toro-Frias1, Pablo Martin Lloret1, Rafael Castro Lopez1, Elisenda Roca1, Francisco Fernandez1, Javier Martin Martinez2, Rosana Rodriguez2 and Montserrat Nafria2

1Instituto de Microelectronica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Spain; 2Department Enginyeria Electronica, Universitat Autonoma de Barcelona, Spain

The availability and efficiency of reliability simulators for analog ICs is becoming critical with the scaling of devices down to the nanometer nodes. Two of the main challenges here are how to simultaneously include different sources of unreliability (such as the time-zero or spatial variability and the aging or time-dependent variability), and how to account for the self-induced changes in device biasing (i.e., stress conditions) caused by the device wear-out. In addition to the already existing stochastic models for time-zero variability, new models for the stochastically-distributed aging mechanisms have been developed in recent years. The combination of these challenges with the need for dealing with a stochastic model for aging, causes a serious computational load issue. This paper presents different methods to accurately include reliability in the simulation of analog ICs while preventing the simulation to become unaffordable in terms of CPU time and load.


An Accurate Yield Estimation Approach for Multivariate Non-normal Data in Semiconductor Quality Analysis

Ingrid Kovacs1, Marina Topa1, Andi Buzo2 and Georg Pelz2

1Technical University of Cluj-Napoca, Romania; 2Infineon Technologies, Germany

The standard multivariate metrics for semiconductor product yield estimation and prediction in production processes usually assume that the parameters contributing to the yield are all normally distributed. However, the data met in production processes is not always multivariate normal. A variety of methods has been developed for multivariate non-normal data, but these usually rely on no statistical information, address only a specific type of multivariate distributions, or become very time consuming from the point of view of the computational cost. Moreover, the sample size of the multivariate data is often insufficient, as only a limited number of measurements are affordable. This results in inaccurate product yield estimation and high variance of the estimates. In this paper, a multivariate distribution fitting methodology is introduced, which, combined with multivariate random data sampling provides a global yield estimation approach. Compared with the simple failure counts method the estimation variance of the proposed method is two times smaller.


Monte Carlo General Sample Classification for Rare Circuit Events Using Random Forest

Reem El-Adawi1 and Mohamed Dessouky2

1Mentor Graphics, Egypt; 2Ain Shams University, Egypt

Yield estimation is becoming a challenging task for circuits that are replicated in millions of instances on a large design (High Replication Circuits, HRC) such as SRAMs and flip flops. This is because a rare event in a circuit cell may have a large impact on the system yield. To achieve high yield in HRC, the failure probability of the individual cell is requested to be very small. Thus the number of Monte Carlo simulations needed to detect a rare event is very large and no longer practical. The statistical blockade has been proposed to decrease the number of Monte Carlo simulations needed using classification of tail points and simulating these points only. The Support Vector Machine (SVM) was used in the classification of tail points. Kernel functions for SVM classifier, linear or radial, were chosen according to the data complexity. In this paper, Random Forest (RF) classifier is used as a general purpose classifier irrespective of the complexity of the data. It is shown that RF classifier provides the same accuracy or improves it without having to know the relationship between the input parameters.


An Ageing-aware Digital Synthesis Approach

Shengyu Duan, Basel Halak and Mark Zwolinski

University of Southampton, United Kingdom

Due to the shrinkage of CMOS technology, wearout mechanisms such as Bias Temperature Instability (BTI) have raised growing concerns for circuit reliability. BTI can cause a threshold voltage shift in CMOS devices and consequently increase circuit delay. This paper presents an ageing-aware gate-level optimization approach that can be used in a modern synthesis process. It aims to optimize a circuit to give improved lifetime reliability under given area and timing constraints. A new sensitivity metric is proposed as a function of area increase, delay reduction, degradation reduction and design constraints. This sensitivity metric can be adjusted to select the most favourable gates in terms of circuit timing, lifetime or both. By iteratively up-sizing the gates with the highest sensitivity, our proposed optimization flow can meet any realizable area and timing constraints, to give up to 3.3x lifetime improvement.

13:20-15:00 Imaging
Room #4 - Plenary room
 Chair: Prof. G. Dundar, Bogazici University, Turkey

An 80 x 25 Pixel CMOS Single-photon Image Sensor with Sub-ns Time Gating for Solid State 3D Scanning

H. Ruokamo1, H. Rapakko1, J. Kostamovaara1

1University of Oulu, Finland

Imager topology with sub-ns time gating for 3D distance measurement application and first measurement results of the prototype are presented. The imager has a fully digital operating principle with single-photon avalanche diode detectors and on-chip narrow gating of pixel groups. The prototype detector has 80 x 25 pixels with a fill factor of 34 % in the sensor area. The chip has been fabricated in a 0.35 um high-voltage process and occupies 5.69 x 5.02 mm2 area.


Photodiode Comparison for Imaging Systems with Harvesting Capabilities

A. Nogier1, A. Peizerat1, G. Sicard1

1CEA-LETI, France

This paper presents a study on photodiodes dedicated to image sensors which merge imaging and harvesting capabilities. This study has led to a VerilogA model of photodiodes dependent on the properties of the CMOS process, photodiodes geometry and illumination. Such model will be useful to make predictions on the behavior of new architectures of photodiodes used in CMOS image sensors embedding harvesting capability.


Optimal Readout Schemes in SPAD-Based Time-Correlated Event Detection Sensor for Quantum Imaging Applications

M. Zarghami1, L. Gasparini1, D. Stoppa1

1Fondazione Bruno Kessler, Italy

CMOS SPAD imagers are potentially good candidates for detection of entangled photons in Quantum Imaging applications thanks to their sub-nanosecond time-resolving capabilities and highly parallel readout. In this context, the low amount of photons that are typically detected corresponds to a very sparse data matrix. Therefore, full readout of raw data is a waste of time and power. We have implemented a sensor architecture for improving the efficiency of the acquisition up to 10% in TDC-based pixel structure. A tunable current source is used per pixel to establish a global current which is pointed out a real-time status of the whole pixel array in terms of triggered SPADs; The proposed solution requires minimum extra pixel electronics, with minimal impact on fill factor since it involves only 2 transistors and allows a frame rate up to 500Kfps.


Miniaturized 64-Channel Single-Photon Timing System

D. Portaluppi1, M. Buttafava1, D. Tamborini1, A. Ruggeri1, F. Villa1

1Politecnico di Milano, Italy

We present a portable 64-channel photon-counting system employing a monolithic array of Single-Photon Avalanche Diodes (SPADs) and a custom-designed Time-to-Digital Converter (TDC), for single-photon counting and timing applications. The system provides state-of-art single-photon detection performance and time-resolved measurement capability, with timing precision down to 100 ps FWHM and linearity better than 2% LSB (RMS). The compact form factor (1'' diameter by 2'' length), extensive customization capabilities, and low power consumption enable its use in applications requiring both high-end single-photon performance and system portability, such as wearable health monitoring, hand-held equipment, and automotive time-of-flight 3D ranging measurement.


Coincidence in SPAD-Based Time-of-Flight Sensors

M. Beer1, O. Schrey1, B. Hosticka1, R. Kokozinski2

1Fraunhofer IMS, Germany; 2University of Duisburg-Essen, Germany

High ambient illumination reduces the range and target detection reliability in light-based 3D sensors. Raising the optical power of the artificial illumination source to overcome the influence of high ambient light is often not possible for systems with flash illumination due to eye safety constraints. The high timing resolution of single-photon avalanche diodes enables the search for photon concurrences in incident photon streams. In this paper a theoretical analysis of coincidence and its benefits for 3D sensors with single-photon avalanche diodes is presented.

15:00-16:20 Company Fair & SMACD Poster Session II
 Chair: Proff. G. Dundar, N. Horta, F. V. Fernandez

A Toolbox for the Symbolic Analysis and Simulation of Linear Analog Circuits

Giorgio Antonino Vazzana1, Alfio Dario Grasso2 and Salvatore Pennisi2

1pureLiFi, United Kingdom; 2University of Catania, Italy

This paper presents a Matlab toolbox for the symbolic analysis and simulation of linear analog circuits. The simulator uses Modified Nodal Analysis (MNA) method to solve linear networks in the s-domain and exploits the Symbolic Math Toolbox for post-processing and numerical simulation. Starting from a SPICE-like netlist, the tool evaluates the circuit node voltages and the current in each independent voltage source. Algorithms for the simplification, with potential order reduction, of symbolic expressions were also developed. The tool is highly customizable and exploits the potentialities of Matlab environment for numerical simulations. A design example confirming the effectiveness of the proposed tool is given.


A Novel Methodology for Electronic Design Exchange

Pradeep Chawda1, Makram Mansour1 and Maurizio Granato2

1Texas Instruments Inc, USA; 2Texas Instruments, Italy

This paper presents a novel methodology to exchange schematic and simulation information between Electronic Design Automation (EDA) tools. The schematic, symbol, model and simulation settings are described using standard extensible markup language (XML) format proposed first time in this paper. The standardization process is discussed and algorithm to generate the standard XML format is described. The proposed algorithm is implemented to exchange designs between WEBENCH, Tina-TI, Altium Designer and Allegro Design Entry CIS and conversion results are presented. The proposed methodology has enabled the design exchange a single click error free process and saved several engineering hours.


An over-the-distance Wireless Battery Charger based on RF Energy Harvesting

Roberto La Rosa1, Giulio Zoppi1, Alessandro Finocchiaro1, Giuseppe Papotto1, Loreto Di Donato2, Gino Sorbello2, Francesco Bellomo2,3, Calogero Alessio Di Carlo2,3 and Patrizia Livreri3

1STMicroelectronics, Italy; 2University of Catania, Italy; 3University of Palermo, Italy

An RF powered receiver silicon IC (integrated circuit) for RF energy harvesting is presented as wireless battery charger. This includes an RF-to-DC energy converter specifically designed with a sensitivity of -18.8 dBm and an energy conversion efficiency of ~45% at 900 MHz with a transmitting power of 0.5W in free space. Experimental results concerned with remotely battery charging using a complete prototype working in realistic scenarios will be shown.


Behavioral Modeling of a Sensor Interface Circuit Including Various Non-Idealities

Sascha Heinssen, Maike Taddiken, Theodor Hillebrand, Steffen Paul and Dagmar Peters-Drolshagen

University of Bremen, Institute of Electrodynamics and Microelectronics, Germany

In modern CMOS processes, several non-ideal influences affect the functionality of integrated circuits. In order to analyze and reduce these influences, time intensive circuit simulations are performed at transistor level. Although numerous non-idealities are considered in such simulations, they cannot be analyzed separately since they are inherent parts of the transistor models and cannot be faded out. In this work, a solution to this problem is presented: the use of Verilog-A/MS behavioral models in combination with Response Surface Modeling. Since error sources can easily be switched on and off in these models, their influence on circuit parameters can be examined individually. Moreover, the required simulation time is drastically reduced by using these models. A 65nm CMOS sensor interface is selected to demonstrate the advantages of the introduced approach. The interface is transferred from transistor to behavioral level before both circuit representations are compared in various simulations.


Optimization of a MEMS Accelerometer Using A Multiobjective Evolutionary Algorithm

Murat Pak1, Francisco Fernandez2 and Gunhan Dundar1

1Department of Electrical and Electronics Engineering, Bogazici University, Istanbul, Turkey; 2Instituto de Microelectronica de Sevilla, IMSE-CNM, CSIC and University of Sevilla, Spain

This paper focuses on the optimization of a fixed-topology MEMS accelerometer sensor using the MOEA/D evolutionary algorithm. Several methodologies have been implemented for the optimization of MEMS sensors. These techniques are either based on sweeping several design parameters to achieve a good performance or focused on the sensitivity analysis to determine the effects of each design parameter in order to find an optimal point. All of these techniques lead to some high performance device designs; however, with the integration of the sensor models into the MOEA/D optimization algorithm, optimal design points can be achieved by using multi-objective optimization. In this work, highly accurate sensor models have been integrated into the optimization loop in order to obtain optimal Pareto Fronts of a MEMS Accelerometer topology. Both of the sensor models and the optimization algorithm has been implemented using Matlab. The results are compared with a commercial design with the same topology and an improvement of 29% of noise performance for a similar sensor area, or an improvement of 25% sensor area for a similar noise performance has been achieved.