Abstract: Nowadays, semiconductor market is constantly demanding higher levels of integration and lower cost systems together with a growing of complexity and performances. In addition, devices with galvanic isolation embedded are gradually replacing the classical architecture with discrete photo-couplers, with the obvious advantage of getting more compact and reliable. Battery chargers and adapters, for example, are experiencing a continuous reduction in size and weight while delivering the same power level, as well as an increased safety level in terms of isolation from the power grid. Furthermore, high-density nanolithography technologies allow progressively reducing data processing core and memory size according to Moore's law, while power devices do not shrink versus lithography, as well. All these trends represent the thrust towards innovative areas of development of System in Package (SiP) solutions. This speech shows different solutions of SiP that address mixed systems with signal devices on one side and high power, high voltage or galvanic isolation devices on the other side. Package optimization, technology selection, complexity and advantages of such solutions versus monolithic approach are also highlighted.
Dr. Francesco Pulvirenti graduated in Electronic Engineering at the University of Pisa in 1989. Born in Catania, Italy in 1964, he joined STMicroelectronics in 1991, where he is currently working as Design Director of the Industrial and Power Conversion Division with the mission to develop new products for Motion Control, Industrial Automation, Battery Charging and Lighting Applications.
He started as design engineer spending around ten years developing Smart Power ICs, Linear Regulators, Switch Mode Power Supply and Power Management respectively for Industrial, Mobile Phone and Computer Applications. In 2001, he moved to Display segment to lead the design of Display Drivers for portable equipment becoming soon Design Director of the Display Division. In 2007, he was appointed Director of the Photovoltaic Business Unit with the task to define and develop new application specific devices for Photovoltaic Market.
He holds more than 50 international patents on Analog and Smart Power ICs, he is also co-author of 13 papers published in international conferences/journals and co-author of the book "Liquid Crystal Display Drivers" edited by Springer in 2009.
Abstract: Today electronic applications are demanding constant form-factor reduction to shrink overall solution size still providing same level or increased functionality. Highly scaled CMOS technologies provides a path for digital size reduction following Moore’s law, but power management does not scale equally well. Semiconductor industry is facing the challenge with a significant increase of system-in-package (SiP) options and solutions leveraging the opportunity this technology gives to effectively use z-dimension and providing flexible design able to fulfil the stringent space constraints. These trends force power electronic designers dealing with multifaceted problems that spans from semiconductor, circuit design theory, thermal simulation and heat transfer, electromagnetics, inductor/transformer design, digital electronics, packaging optimization and material science and leaving engineers facing problems of unprecedented complexity. Particularly form factor reduction through SiP is now being limited by magnetic component size stemming as the largest component in the power modules. In this talk custom magnetic components analysis and model development will be presented. Design of such components is not trivial and should take into account second order effects like frequency dependence of the series resistance due to skin and proximity effects, saturation effects, core losses and self-resonances of the structure due to associated parasitic capacitances and both the analysis and synthesis methodology will be introduced.
Dr. Roberto G. Massolini received the Laurea Degree in Electronic Engineering and the Ph.D. degree in Electronic and Electrical Engineering in 2004 and 2007 from the University of Pavia, Italy. During his Ph.D activity he consulted ST-Microelectronics in the field of Analog Mixed-Signal, ADC architecture models and digitally assisted ADC converters.
He joined National Semiconductor (now Texas Instruments) in 2008 and he worked on HV power conversion for PV, High Frequency Switching Converter and magnetic components design leveraging Quartz, packages features and laminated substrates for LGA and BGA.
He is now part of Texas instruments R&D laboratories (Kilby Labs) and within the labs he currently leads the integrated magnetic development effort and he is actively working on circuit design and optimization, magnetic design and material integration problems. His current research interests include integrated magnetics for power application, fully integrated power converters high voltage applications and packaging for SiP modules.
Abstract: Nowadays five big technology trends, namely, networking, machine to machine, mobile, cloud, big data, are shaping the modern society and all human interaction. At the same time, memories are becoming more and more important in driving the system performance and cost in all electronic systems. Moreover, these trends are requiring a higher memory density lower power and improved performance. So far, since the sixty's, the semiconductor memory industry, DRAM, NOR and NAND, has been able to satisfy such requirements, delivering increasing memory performance and density, along with a continuously reducing cost structure, thanks to a very efficient manufacturing infrastructure and the continuous scaling of dimensions. But as we move into the sub 20nm regime, both NAND and DRAM scaling are becoming increasingly difficult and costly. As a result, the extension of Moore's law can be assured only introducing a different approach, with new revolutionary innovation: from pure scaling of dimensions in planar architectures to fully use the Z-dimension in stacking memory cells in 3D-dimensional arrays. New 3D NAND are now becoming the dominant player in the NVM scenario.
Tommaso Vali is the Senior Director at Micron Semiconductor Italy and has the responsibility of the Avezzano, Padova and Catania Design centers for the design on NVM memories in Europe. He received a degree in electronic engineering at the University of Rome "La Sapienza" in 1987, since then he worked at Texas Instruments and moved to TI Avezzano R&D department as a designer Engineer of MOS circuits in 1994.
He became Senior designer and Distinguished Member of Technical Staff at TI in 1996. In 1998, following Micron Technology Inc. acquisition of all TI memory business, he had increasing responsibilities in the design center as team leader and design Manager for Wireless NOR. Since 2004, he is the Director of the Avezzano design center for NAND design. In 2008, he set up the Padua design center that joined the Avezzano team in NVM design activities. In 2010, the two teams worked to the the first 32Gb 3bpc NAND memory at 32nm in the industry (presented in 2010 at ISSCC, S.Francisco). Since 2015, the Catania design team joined the organization and worked together within the NVM DE teams to the release of a 256Gb 2b/cell 3D NAND and of a 768Gb 3b/cell 3D Floating Gate NAND Flash memory (presented in 2016 at the ISSCC, S.Francisco).